Associative ternary cache for IP routing

A study of a prefix routing cache for Internet IP routing is presented. An output port assignment requires one cache memory access when the assignment is found in cache. The cache array is divided into sets that are of variable size; all entries within a set have the same prefix size. The cache is based on a ternary content addressable memory that matches ones, zeroes and don't care values. Our study shows that an associative ternary cache provides an output port at the speed of one memory access with a very high hit rate. For an 8K entry cache the hit rate ranges from 97.62 to 99.67% on traces of 0.2 to 3.5 million addresses. A port error occurs when the port selected by the cache differs from the port that would have been selected from the routing table. A sampling technique is introduced that reduces the worst port error rate by an order of magnitude (from 0.52 to 0.05%).

[1]  Huan Liu,et al.  Routing prefix caching in network processor design , 2001, Proceedings Tenth International Conference on Computer Communications and Networks (Cat. No.01EX495).

[2]  Nick McKeown,et al.  Routing lookups in hardware at memory access speeds , 1998, Proceedings. IEEE INFOCOM '98, the Conference on Computer Communications. Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies. Gateway to the 21st Century (Cat. No.98.

[3]  José G. Delgado-Frias,et al.  A high-performance encoder with priority lookahead , 2000 .

[4]  Stamatis Vassiliadis,et al.  A Flexible Bit-Pattern Associative Router for Interconnection Networks , 1996, IEEE Trans. Parallel Distributed Syst..

[5]  Huan Liu.  Routing Table Compaction in Ternary CAM , 2002, IEEE Micro.

[6]  Hong-Seok Kim,et al.  66 MHz 2.3 M ternary dynamic content addressable memory , 2000, Records of the IEEE International Workshop on Memory Technology, Design and Testing.

[7]  Nen-Fu Huang,et al.  Design of multi-field IPv6 packet classifiers using ternary CAMs , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).

[8]  Tzi-cker Chiueh,et al.  Cache Memory Design for Internet Processors , 2000, IEEE Micro.

[9]  Günter Karjoth,et al.  Routing on longest-matching prefixes , 1996, TNET.

[10]  David Waitzman,et al.  A 50-Gb/s IP router , 1998, TNET.

[11]  Yakov Rekhter,et al.  An Architecture for IP Address Allocation with CIDR , 1993, RFC.