Hierarchical Specification and Implementation of Combinatorial Algorithms Based on RHS Model *

* This work was partially sponsored by the grant FCT-PRAXIS XXI/BD/21353/99 Abstract The paper introduces RHS model for combinatorial computations that describes partitioning of the problem between reconfigurable hardware (RH) implemented in FPGA and software (S) running on host computer and specifies the respective communication mechanisms. It is shown that such model is very efficient for the considered scope. It follows from two important characteristics of combinatorial problems. Firstly, each particular problem requires very limited number of taskspecific operations that have to be repeated a huge number of times. Secondly, majority of operations is unique, i.e. task-oriented. The proposed specification method is based on graphical language that extends hierarchical graph-schemes.

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