A framework for standard modular simulation :: application to semiconductor wafer fabrication

This paper presents the application of a framework, proposed by the National Institute of Standards and Technology (NIST), for standard modular simulation of semiconductor wafer fabrication facilities or fabs. The application of the proposed framework results in the identification and specification of four different elements in the context of semiconductor fabs: (1) market sector, (2) hierarchical modeling levels, (3) simulation case studies, and (4) models and data. Three examples of the application of the proposed simulation framework are presented by using three semiconductor fab models: the Mini-fab benchmark, Measurement and Improvement of Manufacturing Capacities (MIMAC) data set 1, and the Hewlett-Packard-Wein’s model. In these examples, three different case studies are presented, which consisted in the evaluation of production performance under different workforces, dispatching rules, and wafer lot release rates. The proposed simulation framework is by no means considered complete, and future additions and modifications are expected. Our current and future research is focused on the improvement of the proposed framework (e.g., design and testing of generic case studies) as well as the incorporation of the work being conducted by NIST, within the NIST’s System Integration of Manufacturing Applications (SIMA) program, towards the standardization of data formats for simulation in manufacturing systems.

[1]  Chin Soon Chong,et al.  A simulation based analysis of cycle time distribution, and throughput in semiconductor backend manufacturing , 2001, Comput. Ind..

[2]  F. Chance,et al.  Capacity planning in the face of product-mix uncertainty , 1999, 1999 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat No.99CH36314).

[3]  Randal E. Bryant,et al.  Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.

[4]  Siegfried Selberherr,et al.  Rigorous integration of semiconductor process and device simulators , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  S.I. Marcus,et al.  Optimization of preventive maintenance scheduling for semiconductor manufacturing systems: models and implementation , 2001, Proceedings of the 2001 IEEE International Conference on Control Applications (CCA'01) (Cat. No.01CH37204).

[6]  Yadati Narahari,et al.  Modeling the effect of hot lots in semiconductor manufacturing systems , 1997 .

[7]  C. Enz,et al.  MOS transistor modeling for RF IC design , 2000, IEEE Journal of Solid-State Circuits.

[8]  Tyler Phillips.  AUTOSCHED AP by AutoSimulations , 1998, WSC '98.

[9]  L. Milor,et al.  Simulation of the circuit performance impact of lithography in nanoscale semiconductor manufacturing , 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

[10]  H. Miura,et al.  Mechanical stress control in a VLSI-fabrication process: a method for obtaining the relation between stress levels and stress-induced failures , 2003 .

[11]  M.C. Fu,et al.  A Markov decision process model for capacity expansion and allocation , 1999, Proceedings of the 38th IEEE Conference on Decision and Control (Cat. No.99CH36304).

[12]  Koji Nakamae,et al.  Evaluation of final test process in 64-Mbit DRAM manufacturing system through simulation analysis , 2003, Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI.

[13]  Reha Uzsoy,et al.  A review of production planning and scheduling models in the semiconductor industry , 1994 .

[14]  P. Sánchez,et al.  GENERIC CASE STUDIES FOR MANUFACTURING SIMULATION APPLICATIONS , 2003 .

[15]  Navdeep S. Grewal,et al.  Integrating targeted cycle-time reduction into the capital planning process , 1998, 1998 Winter Simulation Conference. Proceedings (Cat. No.98CH36274).

[16]  J.H. Patel,et al.  Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[17]  Charles R. McLean,et al.  A framework for standard modular simulation , 2002, Proceedings of the Winter Simulation Conference.

[18]  Prathima Agrawal,et al.  A hardware logic simulation system , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Todd LeBaron,et al.  Using simulation to understand capacity constraints and improve efficiency on process tools , 2002, Proceedings of the Winter Simulation Conference.

[20]  M.C. Fu,et al.  Optimal preventive maintenance scheduling in semiconductor manufacturing , 2004, IEEE Transactions on Semiconductor Manufacturing.

[21]  E. Fernandez-Gaucherand,et al.  An algorithm to convert wafer to calendar-based preventive maintenance schedules for semiconductor manufacturing systems , 2003, 42nd IEEE International Conference on Decision and Control (IEEE Cat. No.03CH37475).

[22]  Sunil Kumar,et al.  Queueing network models in the design and analysis of semiconductor wafer fabs , 2001, IEEE Trans. Robotics Autom..

[23]  Manfred Mittler,et al.  Comparison of dispatching rules for semiconductor manufacturing using large facility models , 1999, WSC '99.

[24]  Karl G. Kempf,et al.  A hierarchical approach to production control of reentrant semiconductor manufacturing lines , 2003, IEEE Trans. Control. Syst. Technol..

[25]  Andrzej J. Strojwas,et al.  Perspectives on technology and technology-driven CAD , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  Appa Iyer Sivakumar,et al.  Simulation based cause and effect analysis of cycle time and WIP in semiconductor wafer fabrication , 2002, Proceedings of the Winter Simulation Conference.

[27]  D. J. Medeiros,et al.  OPERATIONAL MODELING & SIMULATION IN SEMICONDUCTOR MANUFACTURING , 1998 .

[28]  Averill M. Law,et al.  Simulation Modeling and Analysis , 1982 .

[29]  Oliver Rose.  CONWIP-like Lot Release for a Wafer Fabrication Facility with Dynamic Load Changes , 2001 .

[30]  Koji Nakamae,et al.  Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application , 1999 .

[31]  Appa Iyer Sivakumar,et al.  Simulation based multiobjective schedule optimization in semiconductor manufacturing , 2002, Proceedings of the Winter Simulation Conference.

[32]  Lawrence M. Wein,et al.  Scheduling semiconductor wafer fabrication , 1988 .

[33]  John W. Fowler,et al.  Using simulation-based scheduling to maximize demand fulfillment in a semiconductor assembly facility , 2002, Proceedings of the Winter Simulation Conference.

[34]  E. Stadlober,et al.  SPICE modeling of process variation using location depth corner models , 2004, IEEE Transactions on Semiconductor Manufacturing.

[35]  Gerald T. Mackulak,et al.  A simulation-based experiment for comparing AMHS performance in a semiconductor fabrication facility , 2001 .

[36]  Lee W. Schruben,et al.  Operational modeling and simulation in semiconductor manufacturing , 1998, 1998 Winter Simulation Conference. Proceedings (Cat. No.98CH36274).

[37]  Leon F. McGinnis,et al.  Distributed simulation with incorporated APS procedures for high-fidelity supply chain optimization , 2001, Proceeding of the 2001 Winter Simulation Conference (Cat. No.01CH37304).

[38]  Y.T. Lee,et al.  A neutral information model for simulating machine shop operations , 2003, Proceedings of the 2003 Winter Simulation Conference, 2003..

[39]  Stanley B. Gershwin,et al.  Scheduling manufacturing systems with work-in-process inventory control: Reentrant systems , 1991 .

[40]  Tsu-Shuan Chang,et al.  Multiobjective scheduling for IC sort and test with a simulation testbed , 1998, ICMTS 1998.

[41]  P.R. Kumar.  Scheduling semiconductor manufacturing plants , 1994, IEEE Control Systems.

[42]  S. S. Panwalkar,et al.  A Survey of Scheduling Rules , 1977, Oper. Res..

[43]  Sanjay Jain,et al.  BOTTLENECK BASED MODELING OF SEMICONDUCTOR SUPPLY CHAINS , 2000 .

[44]  Robert W. Atherton,et al.  Wafer Fabrication: Factory Performance and Analysis , 1995 .

[45]  Reha Uzsoy,et al.  A REVIEW OF PRODUCTION PLANNING AND SCHEDULING MODELS IN THE SEMICONDUCTOR INDUSTRY PART I: SYSTEM CHARACTERISTICS, PERFORMANCE EVALUATION AND PRODUCTION PLANNING , 1992 .

[46]  Chu-Cheow Lim,et al.  Criticality of detailed modeling in semiconductor supply chain simulation , 1999, WSC'99. 1999 Winter Simulation Conference Proceedings. 'Simulation - A Bridge to the Future' (Cat. No.99CH37038).

[47]  Matthias Strobel,et al.  Atomistic simulations and the requirements of process simulator for novel semiconductor devices , 2002 .

[48]  Irfan M. Ovacik,et al.  A framework for supply chain management in semiconductor manufacturing industry , 1995, Seventeenth IEEE/CPMT International Electronics Manufacturing Technology Symposium. 'Manufacturing Technologies - Present and Future'.

[49]  P. R. Kumar,et al.  Re-entrant lines , 1993, Queueing Syst. Theory Appl..

[50]  A. I. Sivakumar,et al.  Multiobjective dynamic scheduling using discrete event simulation , 2001, Int. J. Comput. Integr. Manuf..

[51]  A.A. Rodriguez,et al.  Hierarchical modeling and control for re-entrant semiconductor fabrication lines: a mini-fab benchmark , 1997, 1997 IEEE 6th International Conference on Emerging Technologies and Factory Automation Proceedings, EFTA '97.

[52]  Leon F. McGinnis,et al.  Distributed Supply Chain Simulation as a Decision Support Tool for the Semiconductor Industry , 2003, Simul..

[53]  Stephen John Turner,et al.  Distributed supply-chain simulation using high level architecture , 2001 .

[54]  Charles R. McLean,et al.  Shop Data Model and Interface Specification , 2005 .

[55]  Manfred Mittler,et al.  Reducing The Variance Of Cycle Times In Semiconductor Manufacturing Systems , 1995 .