Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance

Increasing levels of process variation in current technologies have a major impact on power and performance, and result in parametric yield loss. In this work we develop an efficient gate-level approach to accurately estimate the parametric yield defined by leakage power and delay constraints, by finding the joint probability distribution function (jpdf) for delay and leakage power. We consider inter-die variations as well as intra-die variations with correlated and random components. The correlation between power and performance arise due to their dependence on common process parameters and is shown to have a significant impact on yield in high-frequency bins. We also propose a method to estimate parametric yield given the power/delay jpdf that is much faster than numerical integration with good accuracy. The proposed approach is implemented and compared with Monte Carlo simulations and shows high accuracy, with the yield estimates achieving an average error of 2%.

[1]  Kaushik Roy,et al.  Novel sizing algorithm for yield improvement under process variation in nanometer technology , 2004, Proceedings. 41st Design Automation Conference, 2004..

[2]  I. Miller.  Probability, Random Variables, and Stochastic Processes , 1966 .

[3]  C. E. Clark.  The Greatest of a Finite Set of Random Variables , 1961 .

[4]  David Blaauw,et al.  Statistical timing analysis using bounds and selective enumeration , 2003, TAU '02.

[5]  D. J. Hathaway,et al.  Uncertainty-aware circuit optimization , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[6]  S. B. Samaan.  The impact of device parameter variations on the frequency and performance of VLSI chips , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[7]  S. Schwartz,et al.  On the distribution function and moments of power sums with log-normal components , 1982, The Bell System Technical Journal.

[8]  David Blaauw,et al.  Statistical analysis of subthreshold leakage current for VLSI circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  S. G. Duvall,et al.  Statistical circuit modeling and optimization , 2000, 2000 5th International Workshop on Statistical Metrology (Cat.No.00TH8489.

[10]  Michael Orshansky,et al.  Fast statistical timing analysis handling arbitrary delay correlations , 2004, Proceedings. 41st Design Automation Conference, 2004..

[11]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[12]  Hongliang Chang,et al.  Statistical timing analysis considering spatial correlations using a single PERT-like traversal , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[13]  Chandramouli V. Kashyap,et al.  Block-based static timing analysis with uncertainty , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[14]  John G. Proakis,et al.  Probability, random variables and stochastic processes , 1985, IEEE Trans. Acoust. Speech Signal Process..

[15]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[16]  Masahiro Fukui,et al.  A statistical static timing analysis considering correlations between delays , 2001, ASP-DAC '01.

[17]  James D. Meindl,et al.  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.

[18]  Sachin S. Sapatnekar,et al.  Statistical timing analysis considering spatial correlations using a single PERT-like traversal , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[19]  D. Blaauw,et al.  "AU: Timing Analysis Under Uncertainty , 2003, ICCAD 2003.

[20]  David Blaauw,et al.  Parametric yield estimation considering leakage variability , 2004, Proceedings. 41st Design Automation Conference, 2004..

[21]  David Blaauw,et al.  Statistical optimization of leakage power considering process variations using dual-Vth and sizing , 2004, Proceedings. 41st Design Automation Conference, 2004..

[22]  David Blaauw,et al.  AU: Timing Analysis Under Uncertainty , 2003, ICCAD.

[23]  A. Abu-Dayya,et al.  Outage probabilities in the presence of correlated lognormal interferers , 1994 .

[24]  Sarma B. K. Vrudhula,et al.  A methodology to improve timing yield in the presence of process variations , 2004, Proceedings. 41st Design Automation Conference, 2004..

[25]  Natesan Venkateswaran,et al.  First-Order Incremental Block-Based Statistical Timing Analysis , 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  J. H. Cadwell.  The bivariate normal integral , 1951 .

[27]  Vivek De,et al.  Sub-90 nm technologies-challenges and opportunities for CAD , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[28]  Chandramouli V. Kashyap,et al.  Block-based Static Timing Analysis with Uncertainty , 2003, ICCAD.

[29]  Bruno O. Shubert,et al.  Random variables and stochastic processes , 1979 .

[30]  David Blaauw,et al.  /spl tau/AU: Timing analysis under uncertainty , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).