SparkNoC: An energy-efficiency FPGA-based accelerator using optimized lightweight CNN for edge computing

Abstract Over the past few years, Convolution Neural Networks (CNN) have been extensively adopted in broad AI applications and have achieved noticeable effect. Deploying the feedforward inference of CNN on edge devices has now been considered a research hotspot in Edge Computing. In terms of the mobile embedded devices that exhibit constrained resources and power budget, the considerable parameters and computational bottlenecks raised rigorous requirements of deploying the CNN feedforward inference. To address this challenge, the present study develops a lightweight neural network architecture termed as SparkNet, capable of significantly reducing the weight parameters and computation demands. The feasibility of the SparkNet is verified on four datasets, i.e., MINIST, CIFAR-10, CIFAR-100 and SVHN. Besides, the SparkNet is reported exhibiting the ability to effectively compress the convolutional neural network by a factor of 150x. Compared with GPU and ASIC, an FPGA-based accelerator exhibits obvious advantages for its reconfigurable property, flexibility, power efficiency, as well as massive parallelism. Moreover, the network model of the SparkNet and the proposed accelerator architecture are both specifically built for FPGA. The SparkNet on chip (SparkNOC) that maps all the layers of the network to their own dedicated hardware unit for simultaneous pipelined work has been implemented on FPGA. The proposals of this study are assessed by deploying SparkNet model on Intel Arria 10 GX1150 FPGA platform. As revealed from the experimental results, the fully pipelined CNN hardware accelerator achieves 337.2 GOP/s performance under the energy efficiency of 44.48 GOP/s/w, indicating that it outperforms the previous methods.