A 200-MHz CMOS I/Q downconverter

This CMOS in-phase/quadrature (I/Q) downconverter circuit is based on a modified sampling architecture which permits very precise I/Q phase and amplitude balance across the entire 200-MHz bandwidth of operation. At a radio frequency of 201 MHz, the downconverter uses a local oscillator sampling rate of 40 MHz and an intermediate frequency of 1 MHz. The circuit is implemented in a 0.5-/spl mu/m process and has a measured I/Q balance of better than 0.33 dB and 0.7/spl deg/, with a power consumption of 20 mW from a 3-V supply, and a die area of 0.9 mm/sup 2/.