OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain
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Mateus Fogaça | C. Sechen | D. Sylvester | D. Blaauw | A. B. Kahng | V. Srinivas | S. S. Sapatnekar | K. Samadi | M. Woo | A. Kahng | R. Dreslinski | S. Sapatnekar | C. Sechen | D. Blaauw | D. Sylvester | A. Rovinski | S. Reda | P. Pénzes | L. Saul | L. Wang | K. Samadi | Z. Liang | J. Li | Mateus Fogaça | M. Woo | C. Cheng | T. Ajayi | T. Chan | T. Ajayi | T.-B. Chan | C.-K. Cheng | V. A. Chhabria | D. K. Choo | M. Coltella | R. Dreslinski | S. Hashemi | A. Ibrahim | M. Kim | J. Li | Z. Liang | U. Mallappa | P. Penzes | G. Pradipta | S. Reda | A. Rovinski | L. Saul | W. Swartz | D. Urquhart | L. Wang | B. Xu | W. Swartz | A. Ibrahim | B. Xu | V. Srinivas | D. Urquhart | U. Mallappa | S. Hashemi | G. Pradipta | M. Kim | V. Chhabria | M. Coltella
[1] Andrew B. Kahng,et al. Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Derong Liu,et al. Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees , 2018, ISPD.
[3] George Markowsky,et al. A fast algorithm for Steiner trees , 1981, Acta Informatica.
[4] Johann Glaser,et al. Yosys-A Free Verilog Synthesis Suite , 2013 .
[5] Andrew B. Kahng,et al. RePlAce: Advancing Solution Quality and Routability Validation in Global Placement , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Kristina Chodorow,et al. MongoDB - The Definitive Guide: Powerful and Scalable Data Storage , 2019 .
[7] Andrew B. Kahng,et al. TritonRoute: An Initial Detailed Router for Advanced VLSI Technologies , 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[8] Chris C. N. Chu,et al. FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Fogaca Mateus,et al. Quadratic timing objectives for incremental timing-driven placement optimization , 2016 .
[10] Andrew B. Kahng,et al. The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap , 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).