A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order $\Delta \Sigma$ Linearization

This paper presents an 8-bit 1.25-ps resolution reconfigurable Vernier time-to-digital converter (TDC) with a 2-D spiral comparator array and <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulators for linearization. The proposed spiral 2-D comparator array improves both linearity and detection range of the TDC. The quantization errors introduced by digitally tuning delay cells are minimized by using a 2nd-order <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator. The folding point errors commonly seen in 2-D comparator arrays are randomized by using a reconfigurable comparator array controlled by the output of a 2nd-order<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator. The prototype TDC fabricated in a 45-nm silicon on insulator technology consumes 70- to 690-<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power under a 1-V supply at 80-MHz conversion rate. The measured maximum differential nonlinearity/integral nonlinearity across its detectable range are 1.35/1.03 ps without the linearization techniques and 0.31/0.4 ps with the proposed linearization techniques, respectively.

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