Inversion coefficient optimization assisted analog circuit sizing tool

Many analog circuit synthesis tools have emerged over the last two decades in order to combat increased design complexity and reduce the design time. However, the efficiency of these tools (time performance) is still a problem, where solving of a highly nonlinear design problem takes relatively long time even if the process is fully automated. Considering conventional analog circuit design, selection the operating point is essential to achieve a better performance, where inversion coefficient (IC) is commonly utilized as a sizing and biasing independent design parameter, which spans the entire range of saturation region (weak, moderate, strong inversion), and provides a valuable guidance to designer during the design process. Currently, analog circuit sizing tools utilize simplified equations to determine the transistor operating region, where all transistors are forced into the saturation region. Even if all transistors are kept in saturation, the inversion type of transistors has not been taken into account. In this study, a novel analog circuit sizing tool is presented, which facilities the sizing process by optimization of IC to enhance the time to converge.