Delay analysis of neuron-MOS and capacitive threshold-logic

A model for the delay of neuron-PMOS (neu-MOS) and Capacitive Threshold-Logic (CTL) based logic circuits is presented for the first time. It is based on the analysis of the basic neuron-MOS and CTL gate structures. A closed form analytic expression for the delay of the threshold gate is derived. A relation for the delay in terms of an ordinary CMOS inverter delay expressed as a function of the number of inputs to the threshold gate is presented. This relation is shown to be useful in comparing the delay of logic circuit designs based on neu-MOS or CTL and ordinary CMOS.

[1]  Derek Abbott,et al.  Complementary neu-GaAs structure , 2000 .

[2]  Tadashi Shibata,et al.  Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis , 1997 .

[3]  Simon Knowles,et al.  A family of adders , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[4]  Yusuf Leblebici,et al.  A compact high-speed (31,5) parallel counter circuit based on capacitive threshold-logic gates , 1996 .

[5]  Tadahiro Ohmi,et al.  An intelligent MOS transistor featuring gate-level weighted sum and threshold operations , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[6]  H. Yasuura,et al.  A comparison of parallel multipliers with neuron MOS and CMOS technologies , 1996, Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.

[7]  K. Goser,et al.  A low-power and high-performance CMOS fingerprint sensing and encoding architecture , 1998, Proceedings of the 24th European Solid-State Circuits Conference.

[8]  Karem A. Sakallah,et al.  Analytical transient response of CMOS inverters , 1992 .

[9]  Yusuf Leblebici,et al.  A capacitive threshold-logic gate , 1996, IEEE J. Solid State Circuits.

[10]  Werner Weber,et al.  A low-power and high-performance CMOS fingerprint sensing and encoding architecture , 1999 .

[11]  Werner Weber,et al.  On the application of the Neuron MOS transistor principle for modern VLSI design , 1996 .

[12]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .