论文信息 - Fabrication and characteristics of novel load PMOS SSTFT (Stacked Single-crystal Thin Film Transistor) for 3-Dimensional SRAM memory cell

Fabrication and characteristics of novel load PMOS SSTFT (Stacked Single-crystal Thin Film Transistor) for 3-Dimensional SRAM memory cell

The PMOS SSTFT (stacked single-crystal thin film transistor) is developed for achieving the smallest SRAM cell size, such as 45F/sup 2/, and low power mobile applications with the single crystallization technology of the Si thin films on the insulators. The electrical properties of the SSTFT load pMOS are comparable to those of bulk Si Tr. or SOI Tr. For example, Ion/Ioff ratio is nearly 10/sup 7/ and sub-threshold swing is 150 mV/dec. The SNM(Static Noise Margin) value is 650 mV at Vdd=2.0 V and the SSTFT load pMOS lifetime under the HElP stress is over 10 years at 3.0 V operation voltage. The novel S/sup 3/ (stacked single-crystal Si) SRAM cell used the SSTFT pMOS as the load pMOS which is successfully fabricated.

[1] Hyun-Su Kim,et al. Highly manufacturable 100 nm 6T low power SRAM with single poly-Si gate technology , 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).