A hybrid chaos-based pseudo-random bit generator in VHDL-AMS

A new pseudo-random bit generator with an increased level of security and possible resistance to hacker attacks is presented. The generator is based on hybrid (analog and digital) chaotic systems. We also use the VHDL-AMS language in modeling of both the chaotic systems and generator. The 0/1 test for chaos is applied to evaluate the generator's performance.

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