Implementation of a reduced-lattice MIMO detector for OFDM Systems

This paper presents a novel VLSI implementation of a MIMO detector for OFDM systems. The proposed architecture is able to perform both linear MMSE and reduced lattice-aided MIMO detection, making it possible to adjust the balance between performance and power consumption. In order to facilitate real-time detection in reduced lattice mode of operation, a novel fixed-complexity version of the LLL lattice reduction algorithm has been developed, allowing for strict practical timing requirements, such as those specified for new generation IEEE 802.11n wireless LAN systems, to be met. An implementation of the MIMO detector for a system employing up to 4 transmit and receive antennas is described and its complexity and performance are evaluated.

[1]  V. Erceg,et al.  TGn Channel Models , 2004 .

[2]  Dirk Wübben,et al.  Near-maximum-likelihood detection of MIMO systems using MMSE-based lattice reduction , 2004, 2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577).

[3]  Xiaoli Ma,et al.  VLSI Implementation of a Lattice Reduction Algorithm for Low-Complexity Equalization , 2008, 2008 4th IEEE International Conference on Circuits and Systems for Communications.

[4]  Peter A. Hoeher,et al.  Fixed Complexity LLL Algorithm , 2009, IEEE Transactions on Signal Processing.

[5]  Y.H. Hu,et al.  CORDIC-based VLSI architectures for digital signal processing , 1992, IEEE Signal Processing Magazine.

[6]  László Lovász,et al.  Factoring polynomials with rational coefficients , 1982 .