Output stage based high-resolution min/max and rank-order filters

A general architecture for analog implementation of min/max, median, and other rank-order filters is presented. The circuit settles in a single iteration and exhibits low error, even for closely spaced input values or large number of inputs. Increased gain in the global feedback mechanism avoids the large corner error typical of conventional (voltage-follower based) analog winner-take-all and other rank-order filters. The architecture comprises a parallel combination of two-stage amplifiers with common output, where the choice of output stage determines the type of computation performed by the circuit; a common-source with active load generates a min/max filter, while a CMOS inverting amplifier yields a median (or other rank-order) filter. Experimental results are included from a nine-element 45 /spl mu/m /spl times/ 358 /spl mu/m prototype fabricated in 1.6 /spl mu/m CMOS technology.

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