Approximate Karatsuba multiplier for error-resilient applications

Abstract Approximate computing is one of the most trending topics for research since the introduction of error-resilient applications. Approximate arithmetic helps reduce the power consumption, hardware utilization and delay time at the expense of accuracy. Out of all arithmetic operations, multiplication is the most widely used and it forms the crucial section in many applications. Therefore, it is necessary to optimize it as per the requirement of a system. This paper proposes an algorithm for approximate multiplication based on Karatsuba multiplication method which is compared with an existing approximate hybrid Wallace tree multiplier and it is found that the proposed approximate Karatsuba multiplier is better than existing approximate hybrid Wallace Tree multiplier in terms of hardware, latency as well as accuracy. The performance of proposed multiplier is also evaluated with the help of a application of image processing and it is found that proposed multiplier gives similar results as exact multiplier unit. Both the multipliers are implemented in Verilog HDL using Vivado 2018.3.

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