Timed RTOS modeling for embedded system design

With processor speed doubling every 18 months, more and more system functionalities are implemented as software (SW) in the design process of embedded systems. Selecting the "right" RTOS before the SW is developed is very important. In this paper, we present an RTOS modeling tool based on SystemC. It is configurable to support modeling and timed simulation of most popular embedded RTOSs. Timing fidelity is achieved by using delay annotation. The OS timing information is derived from published benchmark data. Experiments show that the accuracy of our approach is able to help designers gain confidence in their RTOS selection. By avoiding using an instruction set simulator, the simulation can be speeded up by more than 3 orders of magnitude. Any other component integrable with SystemC can also be integrated in our simulation environment.

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