论文信息 - Optimal Layout of CMOS Functional Arrays

Optimal Layout of CMOS Functional Arrays

Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design automation systems.

Takao Uehara | William M. van Cleemput | W. M. V. Cleemput | T. Uehara

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