We have successfully demonstrated a 0.34mum2 COB cell 1T1C 64Mb FRAM at 150nm technology node. The minimum signal window between data "1" and data "0" of 64M bit cells was evaluated to 300mV at 85degC, 1.6V VDD. This wide signal window was achieved by introducing advanced anneal technology and optimized capacitor layout, from which the variation of individual cell charge was greatly improved, along with robust 2-D stack capacitor technologies such as 70nm thick MOCVD PZT technology with SRO electrode. In addition, a new reference cell scheme for 1T1C architecture, the multi-reference cell equalizing scheme (MRCE), greatly improved the variation of the reference cell signal for sufficient 1T1C sensing margin. As a result, no single bit failure was found in our 1T1C 64Mb FRAM after 500hour bake at 150degC