Design of a Concatenated Code System and Its FPGA Implementation

WT5”BZ]Concatenated code is an efficient but complex channel coding arithmetic A concatenated coding and decoding circuit is proposed, which can work at two different bit rates and is suitable for applications at low bit rate communication The structures and circuits of the key calculator——Viterbi decoder and RS decoder—— are optimized upon requirements of the system And a new interleaver—buffer control method is presented to decrease the complexity of data transmission and the amount of memories used in the system [WT5HZ]