FATE: a Functional ATPG to Traverse Unstabilized EFSMs

The paper describes a functional ATPG that explores the DUT state space by exploiting an easy-to-traverse extended FSM model. The ATPG engine relies on learning, backjumping and constraint logic programming to deterministically generate test vectors for traversing all transitions of the EFSM

[1]  Fabrizio Ferrandi,et al.  Implicit test generation for behavioral VHDL models , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[2]  Michael S. Hsiao,et al.  Efficient ATPG for design validation based on partitioned state exploration histories , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[3]  Peter Norvig,et al.  Artificial Intelligence: A Modern Approach , 1995 .

[4]  Franco Fummi,et al.  Improving gate-level ATPG by traversing concurrent EFSMs , 2006, 24th IEEE VLSI Test Symposium.

[5]  Michael S. Hsiao,et al.  Efficient sequential atpg for functional rtl circuits , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[6]  F. Fummi,et al.  EFSM Manipulation to Increase High-Level ATPG , 2006 .

[7]  Srivaths Ravi,et al.  Test generation for non-separable RTL controller-datapath circuits using a satisfiability based approach , 2003, Proceedings 21st International Conference on Computer Design.

[8]  Robert M. Hierons,et al.  Expanding an extended finite state machine to aid testability , 2002, Proceedings 26th Annual International Computer Software and Applications.

[9]  David Lee,et al.  Online minimization of transition systems (extended abstract) , 1992, STOC '92.

[10]  Edsger W. Dijkstra,et al.  A note on two problems in connexion with graphs , 1959, Numerische Mathematik.

[11]  Franco Fummi,et al.  Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG? , 2003, Eighth IEEE International High-Level Design Validation and Test Workshop.

[12]  Josef Stoer,et al.  Numerische Mathematik 1 , 1989 .

[13]  Kwang-Ting Cheng,et al.  Efficient conflict-based learning in an RTL circuit constraint solver , 2005, Design, Automation and Test in Europe.

[14]  Glenford J. Myers,et al.  Art of Software Testing , 1979 .

[15]  Ian G. Harris,et al.  Design validation of behavioral VHDL descriptions for arbitrary fault models , 2005, European Test Symposium (ETS'05).

[16]  M. Ümit Uyar,et al.  A method enabling feasible conformance test sequence generation for EFSM models , 2004, IEEE Transactions on Computers.

[17]  Kwang-Ting Cheng,et al.  Automatic generation of functional vectors using the extended finite state machine model , 1996, TODE.

[18]  Daniel D. Gajski,et al.  Essential Issues in Codesign , 1997 .

[19]  Masahiro Fujita,et al.  Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  S. Padmanabhuni.  Extended analysis of intelligent backtracking algorithms for the maximal constraint satisfaction problem , 1999, Engineering Solutions for the Next Millennium. 1999 IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.99TH8411).