Scalable VLSI architectures for full-search block matching algorithms

This paper presents two VLSI architectures for full search block matching motion estimation (ME) algorithm based on overlapped search data flow. The proposed VLSI architectures have three specific features: (1) they contain a processor element (PE) array which provides sufficient computational power and achieves 100% hardware efficiency; (2) they contain stream memory banks which provide scheduled data flow requested by PE for computing mean absolute distortion (MAD); and (3) they both have minimum memory bandwidth to save I/O pin-count.

[1]  Moonkey Lee,et al.  A fast array architecture for block matching algorithm , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[2]  Chen-Yi Lee,et al.  An efficient memory architecture for motion estimation processor design , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[3]  Chen-Yi Lee,et al.  Semi-systolic array based motion estimation processor design , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

[4]  Matthias Schöbinger,et al.  VLSI architecture for a flexible block matching processor , 1995, IEEE Trans. Circuits Syst. Video Technol..

[5]  Chaur-Heh Hsieh,et al.  VLSI architecture for block-matching motion estimation algorithm , 1992, IEEE Trans. Circuits Syst. Video Technol..

[6]  Yu Hen Hu,et al.  A novel modular systolic array architecture for full-search block matching motion estimation , 1995, IEEE Trans. Circuits Syst. Video Technol..