On Uniformly Sampling Traces of a Transition System
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[1] Sasan Iman,et al. The e Hardware Verification Language , 2004, Springer US.
[2] Andreas Kuehlmann,et al. Stimulus generation for constrained random simulation , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[3] Yehuda Naveh,et al. Constraint-Based Random Stimuli Generation for Hardware Verification , 2006, AI Mag..
[4] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[5] Supratik Chakraborty,et al. A Scalable and Nearly Uniform Generator of SAT Witnesses , 2013, CAV.
[6] Dimitris Achlioptas,et al. Fast Sampling of Perfectly Uniform Satisfying Assignments , 2018, SAT.
[7] Leonardo Mendonça de Moura,et al. Generating efficient test sets with a model checker , 2004, Proceedings of the Second International Conference on Software Engineering and Formal Methods, 2004. SEFM 2004..
[8] Harry D. Foster,et al. Assertion-Based Design , 2010 .
[9] Claude Castelluccia,et al. Extending SAT Solvers to Cryptographic Problems , 2009, SAT.
[10] Enrico Macii,et al. Algebric Decision Diagrams and Their Applications , 1997, ICCAD '93.
[11] Vu H. N. Phan,et al. Weighted Model Counting with Algebraic Decision Diagrams , 2019 .
[12] Supratik Chakraborty,et al. Balancing scalability and uniformity in SAT witness generator , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).
[13] Moshe Y. Vardi,et al. ADDMC: Exact Weighted Model Counting with Algebraic Decision Diagrams , 2019, ArXiv.
[14] Mihir Bellare,et al. Uniform Generation of NP-Witnesses Using an NP-Oracle , 2000, Inf. Comput..
[15] Olivier Coudert,et al. Verifying Temporal Properties of Sequential Machines without Building Their State Diagrams , 1990, CAV.
[16] Edmund M. Clarke,et al. Symbolic model checking: 10/sup 20/ states and beyond , 1990, [1990] Proceedings. Fifth Annual IEEE Symposium on Logic in Computer Science.
[17] Rahul Gupta,et al. Knowledge Compilation meets Uniform Sampling , 2018, LPAR.
[18] Michael Sipser,et al. A complexity theoretic approach to randomness , 1983, STOC.
[19] Héctor D. Menéndez,et al. Output Sampling for Output Diversity in Automatic Unit Test Generation , 2022, IEEE Transactions on Software Engineering.
[20] Rahul Gupta,et al. WAPS: Weighted and Projected Sampling , 2019, TACAS.
[21] Marcelo Arenas,et al. Efficient Logspace Classes for Enumeration, Counting, and Uniform Generation , 2019, PODS.
[22] Magdy S. Abadir,et al. A Survey of Hybrid Techniques for Functional Verification , 2007, IEEE Design & Test of Computers.
[23] Sanjit A. Seshia,et al. On Parallel Scalable Uniform SAT Witness Generation , 2015, TACAS.
[24] Wolfgang Roesner,et al. Comprehensive Functional Verification: The Complete Industry Cycle , 2005 .
[25] Leslie G. Valiant,et al. Random Generation of Combinatorial Structures from a Uniform Distribution , 1986, Theor. Comput. Sci..
[26] Edmund M. Clarke,et al. Sequential circuit verification using symbolic model checking , 1991, DAC '90.
[27] Harry Foster,et al. Principles of verifiable RTL design , 2000 .
[28] Larry J. Stockmeyer,et al. The complexity of approximate counting , 1983, STOC.
[29] Harry D. Foster. Trends in functional verification: A 2014 industry study , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[30] Adnan Aziz,et al. Constraint-based verification , 2006 .
[31] Leslie G. Valiant,et al. The Complexity of Computing the Permanent , 1979, Theor. Comput. Sci..