Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
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[1] Elena Trichina,et al. Combinational Logic Design for AES SubByte Transformation on Masked Data , 2003, IACR Cryptol. ePrint Arch..
[2] Ingrid Verbauwhede,et al. A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[3] Sylvain Guilley,et al. The "Backend Duplication" Method , 2005, CHES.
[4] Stefan Mangard,et al. Successfully Attacking Masked AES Hardware Implementations , 2005, CHES.
[5] Daisuke Suzuki,et al. DPA Leakage Models for CMOS Logic Circuits , 2005, CHES.
[6] Anantha P. Chandrakasan,et al. Low Power Digital CMOS Design , 1995 .
[7] Anantha P. Chandrakasan,et al. Low-power CMOS digital design , 1992 .
[8] Ingrid Verbauwhede,et al. Place and Route for Secure Standard Cell Design , 2004, CARDIS.
[9] Stefan Mangard,et al. Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints , 2005, CHES.
[10] Akashi Satoh,et al. An Optimized S-Box Circuit Architecture for Low Power AES Design , 2002, CHES.
[11] Stefan Mangard,et al. Side-Channel Leakage of Masked CMOS Gates , 2005, CT-RSA.
[12] Daisuke Suzuki,et al. Random Switching Logic: A Countermeasure against DPA based on Transition Probability , 2004, IACR Cryptol. ePrint Arch..
[13] Siva Sai Yerubandi,et al. Differential Power Analysis , 2002 .