Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction

Semiconductor design houses rely on third-party foundries to manufacture their integrated circuits (IC). While this trend allows them to tackle fabrication costs, it introduces security concerns as external (and potentially malicious) parties can access critical parts of the designs and steal or modify the Intellectual Property (IP). Embedded FPGA (eFPGA) redaction is a promising technique to protect critical IPs of an ASIC by redacting (i.e., removing) critical parts and mapping them onto a custom reconfigurable fabric. Only trusted parties will receive the correct bitstream to restore the redacted functionality. While previous studies imply that using an eFPGA is a sufficient condition to provide security against IP threats like reverseengineering, whether this truly holds for all eFPGA architectures is unclear, thus motivating the study in this paper. We examine the security of eFPGA fabrics generated by varying different FPGA design parameters. We characterize the power, performance, and area (PPA) characteristics and evaluate each fabric’s resistance to SAT-based bitstream recovery. Our results encourage designers to work with custom eFPGA fabrics rather than off-the-shelf commercial FPGAs and reveals that only considering a redaction fabric’s bitstream size is inadequate for gauging security.

[1]  Hai Zhou,et al.  CycSAT: SAT-based attack on cyclic logic encryptions , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[2]  Sayak Ray,et al.  Evaluating the security of logic encryption algorithms , 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[3]  Brandon Wang,et al.  Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  LiMeng,et al.  IP Protection and Supply Chain Security through Logic Obfuscation , 2019 .

[5]  Pierre-Emmanuel Gaillardon,et al.  OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs , 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

[6]  Luca Benini,et al.  Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes , 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Avesta Sasan,et al.  Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality , 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[8]  Bo Hu,et al.  Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA , 2019, ACM Great Lakes Symposium on VLSI.

[9]  Hai Zhou,et al.  Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking , 2020, ArXiv.

[10]  V. Betz,et al.  FPGA Architecture: Principles and Progression , 2021, IEEE Circuits and Systems Magazine.

[11]  David Z. Pan,et al.  IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits , 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[12]  Avesta Sasan,et al.  LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection , 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[13]  Avesta Sasan,et al.  SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks , 2018, IACR Trans. Cryptogr. Hardw. Embed. Syst..

[14]  Yiorgos Makris,et al.  DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY , 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

[15]  Pierre-Emmanuel Gaillardon,et al.  A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs , 2021, ISPD.

[16]  Ramesh Karri,et al.  Exploring eFPGA-based Redaction for IP Protection , 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[17]  Kevin E. Murray,et al.  VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling , 2020 .

[18]  Meng Li,et al.  KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[19]  Irene G. Karybali,et al.  Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking , 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Ramesh Karri,et al.  ASSURE: RTL Locking Against an Untrusted Foundry , 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Giovanni De Micheli,et al.  FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  RoseJonathan,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2004 .

[23]  Johann Glaser,et al.  Yosys-A Free Verilog Synthesis Suite , 2013 .

[24]  Domenic Forte,et al.  CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme , 2019, IACR Trans. Cryptogr. Hardw. Embed. Syst..

[25]  Houman Homayoun,et al.  InterLock: An Intercorrelated Logic and Routing Locking , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[26]  Zhaokun Han,et al.  Does logic locking work with EDA tools? , 2021, USENIX Security Symposium.

[27]  Stephen M. Trimberger,et al.  FPGA Security: Motivations, Features, and Applications , 2014, Proceedings of the IEEE.

[28]  Anthony J. Yu,et al.  Directional and single-driver wires in FPGA interconnect , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[29]  Hai Zhou,et al.  BeSAT: behavioral SAT-based attack on cyclic logic encryption , 2019, ASP-DAC.

[30]  Lawrence T. Pileggi,et al.  Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion , 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[31]  Jason Luu,et al.  Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect , 2011, FPGA '11.

[32]  Ozgur Sinanoglu,et al.  Breaking CAS-Lock and Its Variants by Exploiting Structural Traces , 2021, IACR Cryptol. ePrint Arch..

[33]  Pierre-Emmanuel Gaillardon,et al.  OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs , 2020, IEEE Micro.

[34]  Ramesh Karri,et al.  A Primer on Hardware Security: Models, Methods, and Metrics , 2014, Proceedings of the IEEE.

[35]  David Wentzlaff,et al.  PRGA: An Open-Source FPGA Research and Prototyping Framework , 2021, FPGA.

[36]  Alex Orailoglu,et al.  Piercing Logic Locking Keys through Redundancy Identification , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[37]  Dirk Koch,et al.  FABulous: An Embedded FPGA Framework , 2021, FPGA.

[38]  Lawrence T. Pileggi,et al.  Top-down Physical Design of Soft Embedded FPGA Fabrics , 2021, FPGA.