A complete test set to diagnose scan chain failures

In this paper, we present a test generation algorithm to improve scan chain failure diagnosis resolution. The proposed test generation algorithm creates a complete test set that guarantees each defective scan cell has unique failing behavior. This algorithm handles stuck-at fault and timing fault models. Problems and solutions that may happen in practical usage are discussed. We further extend the test generation algorithm to handle multiple failing scan chains and designs with embedded scan compression logic. Experimental results show the effectiveness of the proposed diagnostic test generation algorithm.

[1]  Geetani Edirisooriya,et al.  Diagnosis of scan path failures , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[2]  R. J. McNulty,et al.  Partner SRLs for improved shift register diagnostics , 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

[3]  Wu-Tung Cheng,et al.  Using fault model relaxation to diagnose real scan chain defects , 2005, ASP-DAC.

[4]  Kevin Stanley,et al.  High-Accuracy Flush-and-Scan Software Diagnostic , 2001, IEEE Des. Test Comput..

[5]  Janusz Rajski,et al.  Diagnosis with Limited Failure Information , 2006, 2006 IEEE International Test Conference.

[6]  S. Narayanan,et al.  An efficient scheme to diagnose scan chains , 1997, Proceedings International Test Conference 1997.

[7]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.

[8]  Arun Gunda,et al.  Failure analysis for full-scan circuits , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[9]  Srikanth Venkataraman,et al.  A technique for fault diagnosis of defects in scan chains , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[10]  Srikanth Venkataraman,et al.  An algorithmic technique for diagnosis of faulty scan chains , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Yuejian Wu,et al.  Diagnosis of scan chain failures , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[12]  Chia-Hua Lee,et al.  Diagnosis of multiple hold-time and setup-time faults in scan chains , 2005 .

[13]  J. Chien-Mo Li,et al.  Diagnosis of single stuck-at faults and multiple timing faults in scan chains , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Janusz Rajski,et al.  Compressed pattern diagnosis for scan chain failures , 2005, IEEE International Conference on Test, 2005..

[15]  J. Hirase,et al.  Scan chain diagnosis using IDDQ current measurement , 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

[16]  Franco Motika,et al.  Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessor , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[17]  Shi-Yu Huang,et al.  Quick scan chain diagnosis using signal profiling , 2005, 2005 International Conference on Computer Design.

[18]  Sudhakar M. Reddy,et al.  Statistical diagnosis for intermittent scan chain hold-time fault , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[19]  Sandip Kundu.  Diagnosing scan chain faults , 1994, IEEE Trans. Very Large Scale Integr. Syst..