Active On-Die Suppression of Power Supply Noise

An active on-chip circuit is demonstrated in 130nm CMOS for the suppression of on-chip power supply noise due to power distribution resonance. Testchip measurement results indicate up to 40% reduction in power supply noise during clock/power gating at a 2% power and 6% area overhead cost. Oscillation time is reduced by 50%. Simulation results show that comparable overshoot/undershoot and ringing control via on-chip decoupling would require significantly more area and power due to leakage, particularly at 90nm and below

[1]  Raminderpal Singh,et al.  Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers , 2002 .

[2]  Gang Ji,et al.  Design and validation of a power supply noise reduction technique , 2005, IEEE Transactions on Advanced Packaging.

[3]  P. Larsson.  Resonance and damping in CMOS circuits with on-chip decoupling capacitance , 1998 .

[4]  T. J. Cabara,et al.  Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers , 1997 .

[5]  P. Bannon,et al.  A 433 MHz 64 b quad issue RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[6]  Pradip Bose,et al.  Stretching the limits of clock-gating efficiency in server-class processors , 2005, 11th International Symposium on High-Performance Computer Architecture.