Coarse grained reconfigurable architectures in the past 25 years: Overview and classification

Reconfigurable architectures become more popular now general purpose compute performance does not increase as rapidly as before. Field programmable gate arrays are slowly moving into the direction of Coarse Grain Reconfigurable Architectures (CGRA) by adding DSP and other coarse grained IP blocks, general purpose processors become more heterogeneous and include sub-word parallelism and even some reconfigurable logic. In the past 25 years, several CGRAs have been published. In this paper an overview and classification of these architectures is presented. This work also provides a clear definition of CGRAs and identifies topics for future research which are key to unlock the full potential of CGRAs.

[1]  Gerhard Fettweis,et al.  Synchronous Transfer Architecture (STA) , 2004, SAMOS.

[2]  Jaehyuk Huh,et al.  TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP , 2004, TACO.

[3]  André DeHon,et al.  MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[4]  Olivier Sentieys,et al.  DART: a dynamically reconfigurable architecture dealing with future mobile telecommunications constr , 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

[5]  Julio A. de Oliveira Filho,et al.  Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[6]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[7]  Steven Swanson,et al.  The WaveScalar architecture , 2007, TOCS.

[8]  Paolo Bonzini,et al.  EGRA: A Coarse Grained Reconfigurable Architectural Template , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Pierre-Emmanuel Gaillardon,et al.  Reconfigurable Logic : Architecture, Tools, and Applications , 2015 .

[10]  Kiyoung Choi,et al.  Design and Evaluation of a Coarse-Grained Reconfigurable Architecture , 2004 .

[11]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[12]  Henk Corporaal.  Microprocessor architectures - from VLIW to TTA , 1997 .

[13]  Jean Vuillemin,et al.  A reconfigurable arithmetic array for multimedia applications , 1999, FPGA '99.

[14]  André B. J. Kokkeler,et al.  The Chameleon Architecture for Streaming DSP Applications , 2007, EURASIP J. Embed. Syst..

[15]  Vivek Sarkar,et al.  Baring It All to Software: Raw Machines , 1997, Computer.

[16]  Anant Agarwal,et al.  TIERS: Topology IndependEnt Pipelined Routing and Scheduling for VirtualWire™ Compilation , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[17]  Peter M. Athanas,et al.  Colt: an experiment in wormhole run-time reconfiguration , 1996, Other Conferences.

[18]  Jason Cong,et al.  A Fully Pipelined and Dynamically Composable Architecture of CGRA , 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

[19]  Lasse Natvig,et al.  Improving Energy Efficiency through Parallelization and Vectorization on Intel Core i5 and i7 Processors , 2012, 2012 SC Companion: High Performance Computing, Networking Storage and Analysis.

[20]  Sergei Sawitzki,et al.  Astra: An Advanced Space-Time Reconfigurable Architecture , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[21]  Scott A. Mahlke,et al.  Polymorphic Pipeline Array: A flexible multicore accelerator with virtualized execution for mobile multimedia applications , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[22]  Russell Tessier,et al.  Reconfigurable Computing Architectures , 2015, Proceedings of the IEEE.

[23]  Jürgen Becker,et al.  Architecture and application of a dynamically reconfigurable hardware array for future mobile communication systems , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[24]  George Varghese,et al.  Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System , 2001, J. VLSI Signal Process..

[25]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[26]  Jan M. Rabaey,et al.  A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths , 1992 .

[27]  Rudy Lauwereins,et al.  ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.

[28]  Scott A. Mahlke,et al.  CGRA express: accelerating execution using dynamic operation fusion , 2009, CASES '09.

[29]  Spyros Tragoudas,et al.  A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels , 2005, J. Circuits Syst. Comput..

[30]  William J. Dally,et al.  The Imagine Stream Processor , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[31]  John Freeman,et al.  From opencl to high-performance hardware on FPGAS , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

[32]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[33]  Andreas Moshovos,et al.  CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit , 2000, ISCA '00.

[34]  Hee-Seok Kim,et al.  Design evaluation of OpenCL compiler framework for Coarse-Grained Reconfigurable Arrays , 2012, 2012 International Conference on Field-Programmable Technology.

[35]  Kunle Olukotun,et al.  REMARC : Reconfigurable Multimedia Array Coprocessor , 1999 .

[36]  Jürgen Becker.  Field programmable logic and application - 14th international conference (FPL 2004), August 30 - September 1, 2004, Antwerp, Belgium; Proceedings , 2004 .

[37]  Markus Weinhardt,et al.  PACT XPP—A Self-Reconfigurable Data Processing Architecture , 2004, The Journal of Supercomputing.

[38]  William J. Dally,et al.  Smart Memories: a modular reconfigurable architecture , 2000, ISCA '00.

[39]  Luigi Carro,et al.  A reconfigurable heterogeneous multicore with a homogeneous ISA , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[40]  Rainer Leupers,et al.  Handbook of Signal Processing Systems , 2010 .

[41]  Karthikeyan Sankaralingam,et al.  DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing , 2012, IEEE Micro.

[42]  H. Zhang,et al.  A 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing , 2000, IEEE Journal of Solid-State Circuits.

[43]  Kazutoshi Wakabayashi,et al.  C-based SoC design flow and EDA tools: an ASIC and system vendorperspective , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[44]  Carl Ebeling,et al.  Specifying and compiling applications for RaPiD , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[45]  Julio A. de Oliveira Filho,et al.  CRC – Concepts and Evaluation of Processor-Like Reconfigurable Architectures (CRC – Konzepte und Bewertung prozessorartig rekonfigurierbarer Architekturen) , 2007, it Inf. Technol..

[46]  Carl Ebeling,et al.  Architecture design of reconfigurable pipelined datapaths , 1999, Proceedings 20th Anniversary Conference on Advanced Research in VLSI.

[47]  Reiner W. Hartenstein,et al.  A datapath synthesis system for the reconfigurable datapath architecture , 1995, ASP-DAC '95.

[48]  A. G. Hirschbiel,et al.  A Novel ASIC Design Approach based on a New Machine Paradigm , 1990, ESSCIRC '90: Sixteenth European Solid-State Circuits Conference.

[49]  Bernard Pottier,et al.  A holistic approach for tightly coupled reconfigurable parallel processors , 2009, Microprocess. Microsystems.

[50]  Vaishali Tehre,et al.  Survey on Coarse Grained Reconfigurable Architectures , 2012 .

[51]  Jan M. Rabaey,et al.  A reconfigurable data-driven multiprocessor architecture for rapid prototyping of high throughput DSP algorithms , 1993, [1993] Proceedings of the Twenty-sixth Hawaii International Conference on System Sciences.

[52]  Hideharu Amano,et al.  Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases , 2004, FPL.

[53]  Christoforos E. Kozyrakis,et al.  Understanding sources of inefficiency in general-purpose chips , 2010, ISCA.