Performance analysis of electronic commerce multiprocessor server

The performance of an electronic commerce server, i.e. a system running electronic commerce applications, is evaluated in the case of a shared-bus multiprocessor architecture. In particular, we focus on the memory subsystem design. We have analyzed the common case of a system using the MESI coherence protocol, for maintaining coherency among the processor private caches. We have evaluated the miss ratio and the bus traffic of such a system by varying cache size, number of ways, scheduling policy and number of processors, highlighting the relations with different types of data sharing generated by the application or the kernel. We found that passive sharing and false sharing are the major sources of coherence overhead in the case of relatively large caches (over 1M-byte size). False sharing is mainly due to kernel data, and can be eliminated by using appropriate data structure design techniques. A scheduling technique, like cache-affinity can reduce passive sharing but it is not effective in every load condition. Thus, a special coherence protocol could be a better solution to completely eliminate passive sharing overhead and boost performance.