New Techniques for Sequential Software Synthesis from a Polychronous Data Flow Formalism

Much of the design and development of embedded software has been done manually over the years with rigorous posteriori verification steps to ensure correctness of the manually written code. Formalization of requirements to make verification and simulation test bench generation more rigorous are being practiced increasingly, but currently, there is much left to be desired in ensuring complete functional and timing correctness of safety-critical software. Polychronous data flow is a formalism used to express specification and to synthesize sequential software. Existing compilers operating on polychronous specification try to build a hierarchic tree-like intermediate form, bottom-up to relate signals in a design. We propose a Boolean theory based alternative where existing mathematical tools are utilized to generate embedded software from polychronous specification. Relative rates of occurrences of events on signals are identified and a unique top-down order of execution is built. Optimization techniques to improve synthesis time is also provided to enhance the performance of an associated software synthesis tool capable of visually capturing and simulating polychronous specification.