Area-I/O RDL routing for chip-package codesign considering regional assignment

Flip-Chip package provides high density I/Os and better performance in package size, signal/power integrety, and wirelength. Routing on its Re-Distribution Layer (RDL) is one of the most difficult stage in Flip-Chip packaging due to the increasing number of I/Os in modern VLSI designs. Area I/O can shorten the signal path and further increases the I/O density, but the design complexity is also higher. The Area I/O RDL routing problem is introduced in this paper, considering wirelength minimization and chip-package codesign. The proposed algorithm effectively solves the problem. 100% routability is guaranteed, from block ports to I/O pads and from I/O pads to bump pads. The authors propose the concept of regional assignment to evaluate the skew between bumps and balls. It leads the nets to route within neighbor sectors rather than the opposite sector. The experimental results, on 7 industrial designs, show that the router greatly minimizes bump-ball skew compared with [12], with reasonable extra wirelength.

[1]  Chia-Chun Tsai,et al.  Automatic router for the pin grid array package , 1999 .

[2]  Yao-Wen Chang,et al.  Simultaneous block and I/O buffer floorplanning for flip-chip design , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[3]  Chia-Chun Tsai,et al.  NEWS: a net-even-wiring system for the routing on a multilayer PGA package , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Hung-Ming Chen,et al.  An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

[5]  Chia-Chun Tsai,et al.  An automatic router for the pin grid array package , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[6]  Yao-Wen Chang,et al.  Area-I/O flip-chip routing for chip-package co-design , 2008, ICCAD.

[7]  Y. Takeuchi,et al.  Escape routing design to reduce the number of layers in area array packaging , 2000 .

[8]  Zhi-Wei Chen,et al.  Flexible escape routing for flip-chip designs , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

[9]  Jinjun Xiong,et al.  Constraint driven I/O planning and placement for chip-package co-design , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[10]  Chia-Chun Tsai,et al.  An even wiring approach to the ball grid array package routing , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

[11]  Ting-Chi Wang,et al.  Simple yet effective algorithms for block and I/O buffer placement in flip-chip design , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[12]  Rui Shi,et al.  Efficient escape routing for hexagonal array of high density I/Os , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[13]  Yao-Wen Chang,et al.  An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[14]  Yao-Wen Chang,et al.  A routing algorithm for flip-chip design , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..