As computing resource demands continue to escalate in the face of big data, cloud-connectivity and the internet of things, it has become imperative to develop new low-power, scalable architectures. Neuromorphic photonics, or photonic neural networks, have become a feasible solution for the physical implementation of efficient algorithms directly on-chip. This application is primarily due to the linear nature of light and the scalability of silicon photonics, specifically leveraging the wide-scale complementary metal-oxide-semiconductor manufacturing infrastructure used to fabricate microelectronics chips. Current neuromorphic photonic implementations stem from two paradigms: wavelength coherent and incoherent. Here, we introduce a novel architecture that supports coherent and incoherent operation to increase the capability and capacity of photonic neural networks with a dramatic reduction in footprint compared to previous demonstrations. As a proof-of-principle, we experimentally demonstrate simple addition and subtraction operations on a foundry-fabricated silicon photonic chip. Additionally, we experimentally validate an on-chip network to predict the logical 2 bit gates AND, OR, and XOR to accuracies of 96.8%, 99%, and 98.5%, respectively. This architecture is compatible with highly wavelength parallel sources, enabling massively scalable photonic neural networks.
[1]
K. Bergman,et al.
Wafer-Scale-Compatible Substrate Undercut for Ultra-Efficient SOI Thermal Phase Shifters
,
2022,
2022 Conference on Lasers and Electro-Optics (CLEO).
[2]
Anastasios Tefas,et al.
Silicon-integrated coherent neurons with 32GMAC/sec/axon compute line-rates using EAM-based input and weighting cells
,
2021,
2021 European Conference on Optical Communication (ECOC).
[3]
N. Pleros,et al.
Neuromorphic computing through photonic integrated circuits
,
2020,
OPTO.
[4]
Natalia Gimelshein,et al.
PyTorch: An Imperative Style, High-Performance Deep Learning Library
,
2019,
NeurIPS.