Design of robust-path-delay-fault-testable combinational circuits by Boolean space expansion

A procedure for the design of robustly path-delay-fault testable two-level circuits by adding extra inputs to the circuits, using the method called Boolean space expansion is proposed. 100% path delay fault testable two-level circuits are achieved with area overhead in the range of 3% to 30%. A procedure to make the multilevel circuits fully testable is also reported. The results for several ISCAS benchmark circuits are presented.<<ETX>>

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