Hardware Design of a Turbo Product Code Decoder

[1]  Ramesh Pyndiah,et al.  Near-optimum decoding of product codes: block turbo codes , 1998, IEEE Trans. Commun..

[2]  Christophe Jégo,et al.  High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping , 2009, J. Signal Process. Syst..

[3]  Erl-Huei Lu,et al.  A syndrome-based hybrid decoder for turbo product codes , 2010, 2010 International Symposium on Computer, Communication, Control and Automation (3CA).

[4]  Trushita Chaware Turbo product code and AES encryption for wireless communication , 2013, 2013 Nirma University International Conference on Engineering (NUiCONE).

[5]  B. Yamuna,et al.  FPGA Implementation of an Efficient High Speed Max-log-MAP Decoder , 2018, 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI).

[6]  Wen Kuang,et al.  FPGA implementation of a modified turbo product code decoder , 2017, 2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN).

[7]  Yevhen Davydenko,et al.  Hardware-oriented turbo-product codes decoder architecture , 2017, 2017 9th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS).

[8]  Ying-Chang Liang,et al.  A low complexity decoding algorithm for extended turbo product codes , 2008, IEEE Transactions on Wireless Communications.

[9]  Navin Kumar,et al.  Performance of iterative turbo coding with nonlinearly distorted OFDM signal , 2016, 2016 IEEE Annual India Conference (INDICON).

[10]  P. Samundiswary,et al.  Performance Analysis of Turbo Coding with AES for CCSDS Standard , 2014 .

[11]  Junghwan Kim,et al.  An efficient decoding algorithm for block turbo codes , 2001, IEEE Trans. Commun..