A Skein-512 Hardware Implementation

This paper describes our Skein-512 hardware implementation. Skein is a semi-finalist in the NIST hash competition to create SHA-3, with Skein-512 being the primary submission. We compare our implementation of Skein-512 with other published hardware implementations of Skein, and with similar implementations for SHA-1 and SHA-2. We discuss four variations of our critical path to explore the throughput/latency tradeoffs afforded by the Skein algorithm, with the best tradeoff offering throughput of 58Gbps at a latency of 20 clock cycles.

[1]  Máire O'Neill,et al.  Efficient single-chip implementation of SHA-384 and SHA-512 , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[2]  Martin Feldhofer,et al.  High-Speed Hardware Implementations of BLAKE, Blue Midnight Wish, CubeHash, ECHO, Fugue, Gröstl, Hamsi, JH, Keccak, Luffa, Shabal, SHAvite-3, SIMD, and Skein , 2009, IACR Cryptol. ePrint Arch..

[3]  Luigi Dadda,et al.  Quasi-pipelined hash circuits , 2005, 17th IEEE Symposium on Computer Arithmetic (ARITH'05).

[4]  Francis M. Crowe,et al.  Optimisation of the SHA-2 family of hash functions on FPGAs , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[5]  Akashi Satoh,et al.  ASIC hardware focused comparison for hash functions MD5, RIPEMD-160, and SHS , 2005, International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume II.

[6]  Stamatis Vassiliadis,et al.  Cost-Efficient SHA Hardware Accelerators , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Ingrid Verbauwhede,et al.  Throughput Optimized SHA-1 Architecture Using Unfolding Transformation , 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

[8]  Ingrid Verbauwhede,et al.  Iteration Bound Analysis and Throughput Optimum Architecture of SHA-256 (384, 512) for Hardware Implementations , 2007, WISA.

[9]  T. Xanthopoulos,et al.  A high performance SSL IPSEC protocol aware security processor , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..