Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness

The physical unclonable functions (PUFs) are used to provide software as well as hardware security for the cyber-physical systems. They have been used for performing significant cryptography tasks such as generating keys, device authentication, securing against IP piracy, and to produce the root of trust as well. However, they lack in reliability metric. We present a novel approach for improving the reliability as well as the uniqueness of the field programmable gated arrays (FPGAs) based ring oscillator PUF and derive a random number, consuming very small area (< 1%) concerning look-up tables (LUTs). We use frequency profiling method for distributing frequency variations in ring oscillators (RO), spatially placed all across the FPGA floor. We are able to spot suitable locations for RO mapping, which leads to enhanced ROPUF reliability. We have evaluated the proposed methodology on Xilinx -7 series FPGAs and tested the robustness against environmental variations, e.g. temperature and supply voltage variations, simultaneously. The proposed approach achieves significant improvement (i) in uniqueness value upto 49.90%, within 0.1% of the theoretical value (ii) in the reliability value upto 99.70%, which signifies that less than 1 bit flipping has been observed on average, and (iii) in randomness, signified by passing NIST test suite. The response generated through the ROPUF passes all the applicable relevant tests of NIST uniformity statistical test suite.

[1]  Roel Maes Physically Unclonable Functions: Concept and Constructions , 2013 .

[2]  Srinivas Devadas,et al.  Silicon physical random functions , 2002, CCS '02.

[3]  Jorge Guajardo,et al.  Extended abstract: The butterfly PUF protecting IP on every FPGA , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.

[4]  Sergei Vassilvitskii,et al.  k-means++: the advantages of careful seeding , 2007, SODA '07.

[5]  Leonid Bolotnyy,et al.  Physically Unclonable Function-Based Security and Privacy in RFID Systems , 2007, Fifth Annual IEEE International Conference on Pervasive Computing and Communications (PerCom'07).

[6]  Vineet Sahula,et al.  Novel Randomized & Biased Placement for FPGA Based Robust Random Number Generator with Enhanced Uniqueness , 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

[7]  Elaine B. Barker,et al.  A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications , 2000 .

[8]  Qiang Xu,et al.  An FPGA Chip Identification Generator Using Configurable Ring Oscillators , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Arenberg Doctoral,et al.  Physically Unclonable Functions: Constructions, Properties and Applications , 2012 .

[10]  Florian Wilde,et al.  Large scale RO PUF analysis over slice type, evaluation time and temperature on 28nm Xilinx FPGAs , 2018, 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[11]  Peter Simons,et al.  Buskeeper PUFs, a promising alternative to D Flip-Flop PUFs , 2012, 2012 IEEE International Symposium on Hardware-Oriented Security and Trust.

[12]  Masaya Yoshikawa,et al.  Security Evaluation of Ring Oscillator PUF Against Genetic Algorithm Based Modeling Attack , 2019, IMIS.

[13]  Chi-En Daniel Yin,et al.  Design and implementation of a group-based RO PUF , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[14]  Elaine B. Barker,et al.  A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications , 2000 .

[15]  Wolfgang Pribyl,et al.  A microcontroller SRAM-PUF , 2011, 2011 5th International Conference on Network and System Security.

[16]  Ramesh Karri,et al.  A Primer on Hardware Security: Models, Methods, and Metrics , 2014, Proceedings of the IEEE.

[17]  Ning Wang,et al.  A FPGA-based RO PUF with LUT-Based Self-Compare Structure and Adaptive Counter Time Period Tuning , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[18]  Ted G. Lewis,et al.  Generalized Feedback Shift Register Pseudorandom Number Algorithm , 1973, JACM.

[19]  Daniel E. Holcomb,et al.  Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[20]  G. Edward Suh,et al.  Physical Unclonable Functions for Device Authentication and Secret Key Generation , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[21]  Maurits Ortmanns,et al.  In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs , 2019, HOST.

[22]  Mehboob Hasan Ahmed,et al.  An FPGA Chip Identification Generator using Configurable Ring Oscillator , 2016 .

[23]  Róbert Lórencz,et al.  Improved ring oscillator PUF on FPGA and its properties , 2016, Microprocess. Microsystems.

[24]  R. Pappu,et al.  Physical One-Way Functions , 2002, Science.

[25]  Ali Emre Pusane,et al.  Dynamic Programming based grouping method for RO-PUFs , 2013, Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

[26]  Patrick Schaumont,et al.  A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions , 2011, IACR Cryptol. ePrint Arch..

[27]  Abhranil Maiti,et al.  Improved Ring Oscillator PUF: An FPGA-friendly Secure Primitive , 2011, Journal of Cryptology.

[28]  Mitsugu Iwamoto,et al.  Variety enhancement of PUF responses using the locations of random outputting RS latches , 2012, Journal of Cryptographic Engineering.

[29]  Máire O'Neill,et al.  Improved Reliability of FPGA-Based PUF Identification Generator Design , 2017, ACM Trans. Reconfigurable Technol. Syst..

[30]  Maurits Ortmanns,et al.  In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs , 2019, 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[31]  Lior Rokach,et al.  Clustering Methods , 2005, The Data Mining and Knowledge Discovery Handbook.

[32]  Fatemeh Tehranipoor,et al.  Phase calibrated ring oscillator PUF design and implementation on FPGAs , 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

[33]  Zongbin Liu,et al.  FROPUF: How to Extract More Entropy from Two Ring Oscillators in FPGA-Based PUFs , 2016, SecureComm.

[34]  Daniel E. Holcomb,et al.  Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers , 2009, IEEE Transactions on Computers.

[35]  Sauvagya Ranjan Sahoo,et al.  A Modified Configurable RO PUF with Improved Security Metrics , 2015, 2015 IEEE International Symposium on Nanoelectronic and Information Systems.

[36]  Jeroen Delvaux,et al.  Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise , 2013, 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[37]  Ramesh Karri,et al.  Hardware and embedded security in the context of internet of things , 2013, CyCAR '13.

[38]  Jorge Guajardo,et al.  FPGA Intrinsic PUFs and Their Use for IP Protection , 2007, CHES.

[39]  Bin Tang,et al.  Improving the reliability of RO PUF using frequency offset , 2014, 2014 International Conference on Field-Programmable Technology (FPT).

[40]  G. Edward Suh,et al.  Extracting secret keys from integrated circuits , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[41]  Jovan Dj. Golic,et al.  High-Speed True Random Number Generation with Logic Gates Only , 2007, CHES.

[42]  Chi-En Daniel Yin,et al.  Improving PUF security with regression-based distiller , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[43]  Christophe Guyeux,et al.  Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses , 2018, Comput. Sci. Rev..

[44]  Fatemeh Tehranipoor,et al.  A Study of Power Supply Variation as a Source of Random Noise , 2017, 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID).

[45]  ChakrabortyRajat Subhra,et al.  A PUF-Enabled Secure Architecture for FPGA-Based IoT Applications , 2015 .

[46]  Máire O'Neill,et al.  A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations , 2019, IEEE Transactions on Computers.

[47]  Jeroen Delvaux,et al.  Fault Injection Modeling Attacks on 65 nm Arbiter and RO Sum PUFs via Environmental Changes , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[48]  A. S. Mandal,et al.  Novel Placement Bias For Realizing Highly Reliable Physical Unclonable Functions on FPGA , 2018, 2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT).

[49]  Giorgio Di Natale,et al.  Ring oscillators analysis for security purposes in Spartan-6 FPGAs , 2016, Microprocess. Microsystems.

[50]  Gang Qu,et al.  Temperature-aware cooperative ring oscillator PUF , 2009, 2009 IEEE International Workshop on Hardware-Oriented Security and Trust.

[51]  Debdeep Mukhopadhyay,et al.  A PUF-Enabled Secure Architecture for FPGA-Based IoT Applications , 2015, IEEE Transactions on Multi-Scale Computing Systems.

[52]  D. Rubin,et al.  Maximum likelihood from incomplete data via the EM - algorithm plus discussions on the paper , 1977 .

[53]  Máire O'Neill,et al.  A machine learning attack resistant multi-PUF design on FPGA , 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

[54]  Stephen A. Benton,et al.  Physical one-way functions , 2001 .

[55]  Patrick Schaumont,et al.  A large scale characterization of RO-PUF , 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[56]  Rajat Subhra Chakraborty,et al.  Model building attacks on Physically Unclonable Functions using genetic programming , 2013, 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[57]  Mohammad S. Hashmi,et al.  Compact Implementations of FPGA-based PUFs with Enhanced Performance , 2017, 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID).

[58]  Gang Qu,et al.  A Machine Learning Attack Resistant Dual-mode PUF , 2018, ACM Great Lakes Symposium on VLSI.

[59]  Srinivas Devadas,et al.  Modeling attacks on physical unclonable functions , 2010, CCS '10.