An advanced diagnostic method for delay faults in combinational faulty circuits
暂无分享,去创建一个
[1] Patrick Girard,et al. An implicit delay fault simulation method with approximate detection threshold calculation , 1993, Proceedings of IEEE International Test Conference - (ITC).
[2] Anantha P. Chandrakasan,et al. Low-power CMOS digital design , 1992 .
[3] John A. Waicukauski,et al. Fault Diagnosis in an LSSD Environment , 1981, ITC.
[4] Michael D. Ciletti,et al. A variable observation time method for testing delay faults , 1991, DAC '90.
[5] Sudhakar M. Reddy,et al. On the computation of the ranges of detected delay fault sizes , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[6] Nandakumar Nityananda Tendolkar. Analysis of Timing Failures Due to Random AC Defects in VLSI Modules , 1985, DAC 1985.
[7] John A. Waicukauski,et al. On computing the sizes of detected delay faults , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] Sudhakar M. Reddy,et al. On the detection of delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[9] David Hung-Chang Du,et al. Path sensitization in critical path problem , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[10] Barry K. Rosen,et al. Delay test generation. I. Concepts and coverage metrics , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[11] M. R. Mercer,et al. A statistical model for delay-fault testing , 1989, IEEE Design & Test of Computers.
[12] Gordon L. Smith,et al. Model for Delay Faults Based upon Paths , 1985, ITC.
[13] Janusz Rajski,et al. A method of fault analysis for test generation and fault diagnosis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[14] J.A. Waicukauski,et al. Failure diagnosis of structured VLSI , 1989, IEEE Design & Test of Computers.
[15] Janusz Rajski,et al. A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[16] Michael D. Ciletti,et al. A Simplified Six-Waveform Type Method for Delay Fault Testing , 1989, 26th ACM/IEEE Design Automation Conference.
[17] F. Brglez,et al. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .
[18] Premachandran R. Menon,et al. Critical Path Tracing - An Alternative to Fault Simulation , 1983, 20th Design Automation Conference Proceedings.
[19] John P. Hayes,et al. Digital Simulation with Multiple Logic Values , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[20] Sudhakar M. Reddy,et al. On the fault coverage of delay fault detecting tests , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..
[21] Patrick Girard,et al. A novel approach to delay-fault diagnosis , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[22] C. Landrault,et al. A reconvergent fanout analysis for the CPT algorithm used in delay-fault diagnosis , 1993, Proceedings ETC 93 Third European Test Conference.
[23] Robert A. Rasmussen,et al. Delay test generation , 1977, DAC '77.