The Test Access Port and Boundary Scan Architecture
暂无分享,去创建一个
[1] Najmi T. Jarwala,et al. A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[2] Paul Keating,et al. Integrating Guided Probe and Fault Dictionary: An Enhanced Diagnostic Approach , 1986, International Test Conference.
[3] Wolfgang O. Budde. Modular testprocessor for VLSI chips and high-density PC boards , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] John Hadjilogiou,et al. Built-in test strategy for next generation military avionic hardware , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[5] Alfred V. Aho,et al. An optimization technique for protocol conformance test generation based on UIO sequences and rural Chinese postman tours , 1991, IEEE Trans. Commun..
[6] Mark F. Lefebvre. Functional test and diagnosis: a proposed JTAG sample mode scan tester , 1990, Proceedings. International Test Conference 1990.
[7] Vinod K. Agarwal,et al. Testing and diagnosis of interconnects using boundary scan architecture , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[8] Donald Komonytsky,et al. LSI Self-Test Using Level Sensitive Scan Design and Signature Analysis , 1982, ITC.
[9] Edward F. Moore,et al. Gedanken-Experiments on Sequential Machines , 1956 .
[10] Don Sterba,et al. ATPG issues for board designs implementing boundary scan , 1990, Proceedings. International Test Conference 1990.
[11] Benoit Nadeau-Dostie,et al. Testing of glue logic interconnects using boundary scan architecture , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[12] Lynn Conway,et al. Introduction to VLSI systems , 1978 .
[13] Frans de Jong. Boundary scan test used at board level: moving towards reality , 1990, ITC.
[14] Clay S. Gloster,et al. Hardware-based weighted random pattern generation for boundary scan , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[15] David R. Resnick. Real World Built-in Test for VLSI , 1986, COMPCON.
[16] Geoffrey Mills. On the board , 1981 .
[17] Hideo Fujiwara,et al. On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.
[18] Edward J. McCluskey,et al. Hybrid designs generating maximum-length sequences , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[19] Lubomyr M. Zobniw,et al. Selective Controllability: A Proposal for Testing and Diagnosis , 1978, 15th Design Automation Conference.
[20] Paul H. Bardell,et al. Self-Testing of Multichip Logic Modules , 1982, International Test Conference.
[21] Gordon D. Robinson,et al. Scan test architectures for digital board testers , 1991, J. Electron. Test..
[22] Lee Whetsel. Event qualification: a gateway to at-speed system testing , 1990, Proceedings. International Test Conference 1990.
[23] Najmi T. Jarwala,et al. The boundary-scan master: target applications and functional requirements , 1990, Proceedings. International Test Conference 1990.
[24] David Bryan,et al. Automated synthesis for testability , 1989 .
[25] Peter Hansen. New Techniques for Manufacturing Test and Diagnosis of LSSD Boards , 1983, ITC.
[26] W. David Ballew,et al. Board-level boundary-scan: regaining observability with an additional IC , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[27] Thomas W. Williams,et al. A logic design structure for LSI testability , 1977, DAC '77.
[28] David L. Landis,et al. Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration , 1990, Proceedings. International Test Conference 1990.
[29] Edward McCluskey,et al. Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.
[30] Prabhakar Goel,et al. Electronic Chip-In-Place Test , 1982, DAC 1982.
[31] David L. Landis. A self-test system architecture for reconfigurable WSI , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[32] Ch Hao,et al. Computer Aided Structured Design for Testability of ASlCs , 1989 .
[33] Gordon D. Robinson,et al. Interconnect testing of boards with partial boundary scan , 1990, Proceedings. International Test Conference 1990.
[34] K.P. Parker. The impact of boundary scan on board test , 1989, IEEE Design & Test of Computers.
[35] Alfred L. Crouch,et al. Prototype testing simplified by scannable buffers and latches , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[36] Frans P. M. Beenker. Systematic and Structured Methods for Digital Board Testing , 1985, ITC.
[37] Jacob A. Abraham,et al. The economics of scan design , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[38] J. Turino. IEEE P1149 Proposed Standard Testability Bus-An update with case histories , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.
[39] David L. Landis,et al. Evaluation of system BIST using computational performance measures , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[40] E.J. McCluskey,et al. A self-test and self-diagnosis architecture for boards using boundary scans , 1989, [1989] Proceedings of the 1st European Test Conference.
[41] Melvin A. Breuer,et al. A test and maintenance controller for a module containing testable chips , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[43] Peter Hansen. Converting Device Test Vectors to an In-Circuit Board Test Environment , 1985, ITC.
[44] Kenneth R. Bowden,et al. The Modern Fault Dictionary , 1985, ITC.
[45] Peter S. Bottorff,et al. Test generation for large logic networks , 1977, DAC '77.
[46] D. Patterson,et al. Wafer scale integration , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[47] Clay S. Gloster,et al. Boundary scan with cellular-based built-in self-test , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[48] Najmi T. Jarwala,et al. A unified theory for designing optimal test generation and diagnosis algorithms for board interconnects , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[49] William H. Kautz,et al. Testing for Faults in Wiring Networks , 1974, IEEE Transactions on Computers.
[50] Johnny J. LeBlanc,et al. LOCST: A Built-In Self-Test Technique , 1984, IEEE Design & Test of Computers.
[51] A. H. Anderson,et al. RVLSI applications and physical design , 1989, [1989] Proceedings International Conference on Wafer Scale Integration.
[52] Y. Zorian,et al. Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[53] Peter Hansen,et al. Testing conventional logic and memory clusters using boundary scan devices as virtual ATE channels , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[54] David L. Landis,et al. Influence of Built-In Self Test on the Performance of Fault Tolerant VLSI Multiprocessors , 1987, ICPP.
[55] Johann Maierhofer. Hierarchical self-test concept based on the JTAG standard , 1990, Proceedings. International Test Conference 1990.
[56] Subrata Dasgupta,et al. Chip Partitioning Aid: A Design Technique for Partitionability and Testability in VLSI , 1984, 21st Design Automation Conference Proceedings.
[57] John A. Waicukauski,et al. An LSSD Pseudo Random Pattern Test System , 1983, ITC.
[58] M. A. Breuer,et al. A universal test and maintenance controller for modules and boards , 1989 .
[59] Anthony P. Ambler,et al. Cost analysis of test method environments , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[60] R. Frankel,et al. SLASH-An RVLSI CAD system , 1989, [1989] Proceedings International Conference on Wafer Scale Integration.
[61] P. W. Wyatt,et al. Restructurable VLSI-a demonstrated wafer-scale technology , 1989, [1989] Proceedings International Conference on Wafer Scale Integration.
[62] D. van de Lagemaat. Testing multiple power connections with boundary scan , 1989 .
[63] P. P. Fasang. Boundary scan and its application to analog-digital ASIC testing in a board/system environment , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.
[64] S. DasGupta,et al. LSI chip design for testability , 1978, 1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[65] B. I. Dervisoglu. Using scan technology for debug and diagnostics in a workstation environment , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[66] Edward J. McCluskey,et al. Design for Autonomous Test , 1981, IEEE Transactions on Computers.
[67] F.P.M. Beenker,et al. Macro Testing: Unifying IC And Board Test , 1986, IEEE Design & Test of Computers.
[68] Prabhakar Goel,et al. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.
[69] M. Breuer,et al. A methodology for the design of hierarchically testable and maintainable digital systems , 1988 .
[70] Hans G. Kerkhoff,et al. Designing and implementing an architecture with boundary scan , 1990, IEEE Design & Test of Computers.
[71] Harry Bleeker,et al. Testing a Board Loaded with Leaded and Surface Mounted Components , 1986, ITC.
[72] Douglas W. Stout,et al. Boundary-scan design principles for efficient LSSD ASIC testing , 1990 .
[73] Franc Brglez,et al. Accelerated Transition Fault Simulation , 1987, 24th ACM/IEEE Design Automation Conference.
[74] Jenq-Neng Hwang,et al. Wavefront Array Processors-Concept to Implementation , 1987, Computer.
[75] Jack H. Arabian,et al. Implications of the Technique for Dynamic High Speed Functional Testing , 1982, ITC.
[76] F. Brglez,et al. Boundary scan with built-in self-test , 1989, IEEE Design & Test of Computers.
[77] Prabhakar Goel. Test generation costs analysis and projections , 1980, DAC '80.
[78] Stig Oresjo,et al. A language for describing boundary scan devices , 1991, J. Electron. Test..
[79] S. Al-Arian,et al. Wafer scale architecture for an FFT processor , 1989, IEEE International Symposium on Circuits and Systems,.
[80] H.G. Kerkhoff,et al. Design and implementation of a hierarchical testable architecture using the boundary scan standard , 1989, [1989] Proceedings of the 1st European Test Conference.
[81] Michael A. Jones,et al. Design for Access. , 1978 .
[82] Melvin A. Breuer,et al. Concurrent control of multiple BIT structures , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[83] Paul Wagner,et al. INTERCONNECT TESTING WITH BOUNDARY SCAN , 1987 .