Analysis of multi-gigabits signal integrity through clock H-tree

The H-tree interconnect network is frequently used for the clock signal sharing in the microelectronic systems. Due to the increase of complexity and operating processing data speed, these interconnect effects can bottleneck the technological advancement. Hence, more accurate interconnect modelling methods are necessary for electronic designers. For this reason, a simple and accurate ultra-wide band (UWB) model of multilevel distributed interconnection clock trees as a single input multiple outputs (SIMO) system is developed in this article. Very accurate single input single output (SISO) model transfer functions are derived. This method allows the signal integrity prediction regarding the distributed H-tree characteristics including the source and load impedances. In order to demonstrate the relevance of model developed, analyses of two- and three-level tree networks were performed. Distributed H-tree realistic devices formed by sub-millimetre physical length lines for applications for standardised Printed Circuit Board (PCB) interconnections were experimented numerically. The piece of lines constituting the trees is modelled by UWB RLCG network from DC to 8 GHz which takes into account the frequency dispersions and dielectric loss effects. Thus, excellent correlations between simulations and the results from the models proposed were observed both in frequency and time domains regarding 2.5 Gbits/s clock input. Copyright © 2012 John Wiley & Sons, Ltd.

[1]  Kaushik Roy,et al.  Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Jason Cong,et al.  Performance optimization of VLSI interconnect layout , 1996, Integr..

[3]  Lawrence T. Pileggi,et al.  The Elmore Delay as a Bound for RC Trees with Generalized Input Signals , 1995, 32nd Design Automation Conference.

[4]  C. A. Marinov,et al.  The energy bounds in RC circuits , 1999 .

[5]  Anantha Chandrakasan,et al.  A bus energy model for deep submicron technology , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Stephen P. Boyd,et al.  Optimizing dominant time constant in RC circuits , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Payman Zarkesh-Ha,et al.  Interconnect opportunities for gigascale integration , 2002, IBM J. Res. Dev..

[8]  Blaise Ravelo,et al.  TRANSIENT RESPONSE CHARACTERIZATION OF THE HIGH-SPEED INTERCONNECTION RLCG-MODEL FOR THE SIGNAL INTEGRITY ANALYSIS , 2011 .

[9]  Ying-Khai Teh,et al.  A study and design of CMOS H-Tree clock distribution network in system-on-chip , 2009, 2009 IEEE 8th International Conference on ASIC.

[10]  Cheng-Kok Koh,et al.  UST/DME: a clock tree router for general skew constraints , 2000, TODE.

[11]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[12]  W. Bandurski,et al.  Effect of inductance on interconnect propagation delay in VLSI circuits , 2004, Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects.

[13]  Guoqing Chen,et al.  Transient Response of a Distributed RLC Interconnect Based on Direct Pole Extraction , 2009, J. Circuits Syst. Comput..

[14]  Eby G. Friedman,et al.  Exponentially tapered H-tree clock distribution networks , 2005, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[15]  Ian Galton,et al.  Tree-Structured DEM DACs with Arbitrary Numbers of Levels , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Martine D. F. Schlag,et al.  Bounds on signal delay in RC mesh networks , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Yan-Chyuan Shiau,et al.  Generic linear RC delay modeling for digital CMOS circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Woong Hwan Ryu.  DesignCon 2006 A Co-design Methodology of Signal Integrity and Power Integrity , 2005 .

[19]  Yehea I. Ismail,et al.  Serial-link bus: a low-power on-chip bus architecture , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[20]  Jeffrey A. Davis,et al.  Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  Markku Rouvala,et al.  Multi-gigabit serial link emissions and mobile terminal antenna interference , 2009, 2009 IEEE Workshop on Signal Propagation on Interconnects.

[22]  E. Friedman,et al.  Equivalent Elmore delay for RLC trees , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[23]  Yehea Ismail,et al.  Fast and accurate simulation of tree structured interconnect , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[24]  Bo Fu,et al.  On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[25]  Dimitrios Velenis,et al.  Parameter variations and crosstalk noise effects on high performance H-tree clock distribution networks , 2008 .

[26]  Albert E. Ruehli.  Circuit analysis, simulation, and design: general aspects of circuit analysis and design , 1986 .

[27]  Marios C. Papaefthymiou,et al.  A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[28]  Andrew B. Kahng,et al.  A power-constrained MPU roadmap for the International Technology Roadmap for Semiconductors (ITRS) , 2009, 2009 International SoC Design Conference (ISOCC).

[29]  André Ivanov,et al.  Jitter models for the design and test of Gbps-speed serial interconnects , 2004, IEEE Design & Test of Computers.

[30]  Gerard V. Kopcsay,et al.  High-Speed Signal Propagation on Lossy Transmission Lines , 1990, IBM J. Res. Dev..

[31]  Andrew B. Kahng,et al.  An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[32]  J. Wells,et al.  Faster than fiber: The future of multi-G/s wireless , 2009, IEEE Microwave Magazine.

[33]  Eby G. Friedman,et al.  Buffer sizing for delay uncertainty induced by process variations , 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

[34]  Y. Awatsuji,et al.  Two-dimensional H-tree parallel optical interconnect for two-dimensional image by using optical iterative processing , 2001, IEEE Photonics Technology Letters.

[35]  B. Ravelo,et al.  Application of negative group delay active circuits to reduce the 50% propagation Delay of RC-line model , 2008, 2008 12th IEEE Workshop on Signal Propagation on Interconnects.

[36]  Kwyro Lee,et al.  A unified RLC model for high-speed on-chip interconnects , 2003 .

[37]  Yun Bai,et al.  Optimization of Driver Preemphasis for On-Chip Interconnects , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[38]  Soyoung Kim,et al.  Modeling and screening on-chip interconnect inductance , 2004 .

[39]  B. Ravelo,et al.  Equalization of interconnect propagation delay with negative group delay active circuits , 2007, 2007 IEEE Workshop on Signal Propagation on Interconnects.

[40]  Vernon L. Chi.  Salphasic Distribution of Clock Signals for Synchronous Systems , 1994, IEEE Trans. Computers.

[41]  W. Maichen.  When digital becomes analog - Interfaces in high speed test , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[42]  Yehea I. Ismail,et al.  Figures of merit to characterize the importance of on-chip inductance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[43]  Chien-Nan Jimmy Liu,et al.  A Tree-Topology Multiplexer for Multiphase Clock System , 2009, IEEE Trans. Circuits Syst. I Regul. Pap..

[44]  Blaise Ravelo,et al.  A New Technique of Interconnect Effects Equalization by Using Negative Group Delay Active Circuits , 2010 .

[45]  Blaise Ravelo,et al.  Experimental validation of the RC-interconnect effect equalization with negative group delay active circuit in planar hybrid technology , 2009, 2009 IEEE Workshop on Signal Propagation on Interconnects.

[46]  V. C. Prasad,et al.  Delay-time sensitivity in linear RC tree , 1987 .

[47]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[48]  John L. Wyatt,et al.  Improved Signal Delay Bounds for RC Tree Networks , 1986 .

[49]  Rashaunda Henderson,et al.  Three-dimensional high-frequency distribution networks. II. Packaging and integration , 2000 .