Thermal characterization of LDMOS transistors for accelerating stress testing

The time to market is a major concern in the high-technology industry and when designing new products, the development cycle time becomes critical. Indeed, when a delay occurs in the development schedule, the potential market share of the designed product can be drastically decreased. In this context, developing accelerated stress testing (AST) in order to assess quickly the long-term behavior of a semiconductor becomes extremely useful. In this paper we show an example of how thermal characterization including simulation can be used to define a consistent AST for power ICs.

[1]  Der-Gao Lin,et al.  A novel LDMOS structure with a step gate oxide , 1995, Proceedings of International Electron Devices Meeting.

[2]  V. Sarihan,et al.  Accelerated life testing for micro-machined chemical sensors , 1998 .

[3]  G. Charitat,et al.  Clamped inductive switching of LDMOST for smart power IC's , 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).

[4]  J.-M. Dorkel,et al.  Rapid thermal modeling for smart-power and integrated multichip power circuit design , 1996, 8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings.

[5]  B. Murari Reliability of smart power devices , 1997 .

[6]  D. L. Blackburn,et al.  Power MOSFET failure revisited , 1988, PESC '88 Record., 19th Annual IEEE Power Electronics Specialists Conference.

[7]  Alfred E. Brenner,et al.  Moore's Law , 1997, Science.