TSUNAMI: a path oriented scheme for algebraic test generation
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[1] C. Y. Lee. Representation of switching circuits by binary-decision programs , 1959 .
[2] J. Paul Roth,et al. Diagnosis of automata failures: a calculus and a method , 1966 .
[3] F. F. Sellers,et al. Analyzing Errors with the Boolean Difference , 1968, IEEE Transactions on Computers.
[4] Oscar H. Ibarra,et al. Polynomially Complete Fault Detection Problems , 1975, IEEE Transactions on Computers.
[5] Sheldon B. Akers. A Logic System for Fault Test Generation , 1976, IEEE Transactions on Computers.
[6] Sheldon B. Akers,et al. Binary Decision Diagrams , 1978, IEEE Transactions on Computers.
[7] Prabhakar Goel,et al. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.
[8] Hideo Fujiwara,et al. On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.
[9] F. Brglez,et al. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .
[10] F. Brglez,et al. A neutral netlists of 10 combinational circuits and a target translator in FORTRAN , 1985 .
[11] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[12] M. Ray Mercer,et al. A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.
[13] CATAPULT: concurrent automatic testing allowing parallelization and using limited topology , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[14] K. Karplus. REPRESENTING BOOLEAN FUNCTIONS WITH IF-THEN-ELSE DAGs , 1988 .
[15] Michael H. Schulz,et al. SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[16] David Bryan,et al. Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.
[17] Tracy Larrabee. Efficient generation of test patterns using Boolean difference , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[18] Michael H. Schulz,et al. Improved deterministic test pattern generation with applications to redundancy identification , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[19] John A. Waicukauski,et al. ATPG for ultra-large structured designs , 1990, Proceedings. International Test Conference 1990.
[20] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[21] Wilfried Daehn,et al. Contest: a fast ATPG tool for very large combinational circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[22] Michael L. Bushnell,et al. SEARCH STATE EQUIVALENCE FOR REDUNDANCY IDENTIFICATION AND TEST GENERATION , 1991, 1991, Proceedings. International Test Conference.
[23] Nagisa Ishiura,et al. Shared binary decision diagram with attributed edges for efficient Boolean function manipulation , 1990, 27th ACM/IEEE Design Automation Conference.
[24] Randal E. Bryant,et al. Efficient implementation of a BDD package , 1991, DAC '90.
[25] Dhiraj K. Pradhan,et al. Recursive Learning: An attractive alternative to the decision tree for test generation in digital ci , 1992, Proceedings International Test Conference 1992.
[26] Leendert M. Huisman,et al. A small test generator for large designs , 1992, Proceedings International Test Conference 1992.
[27] Vishwani D. Agrawal,et al. A transitive closure algorithm for test generation , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..