In this paper we present a fault tolerant (FT) technique for programmable interconnect resources in FPGAs. We take advantage of faulty interconnect reuse, and present a new method for dealing with multiple interconnect faults. For our approach, the system application in the FPGA is on-line and executing while testing, diagnosis, and FT reconfiguration take place. We reuse faulty interconnect resources whenever possible to eliminate FT reconfiguration and to reduce the use of spare interconnects. When FT reconfiguration is required, our approach is based on partial, incremental routing that uses a routing window to reduce reconfiguration time, incremental configuration file size, and incremental configuration file download time. We also include the optional use of parameterizable, preallocated spare interconnect resources. Our multi-staged, interconnect FT techniques are integrated with our logic FT techniques presented in [8], and have been successfully implemented on the ORCA 2CA series of FPGAs from Lucent Technologies.