Automatic verification of scheduling results in high-level synthesis

A method for the fully automatic equivalence verification of a design before and after the scheduling step of high-level synthesis is presented. The technique is applicable to the results of advanced scheduling methods like AFAP and DLS, which work on cyclic control flows, as well as to pipelined designs.

[1]  C. A. J. van Eijk,et al.  Sequential equivalence checking without state space traversal , 1998, DATE.

[2]  David Cyrluk,et al.  Inverting the Abstraction Mapping: A Methodology for Hardware Verification , 1996, FMCAD.

[3]  Anand Raghunathan,et al.  Verification of RTL generated from scheduled behavior in a high-level synthesis flow , 1998, ICCAD.

[4]  Ahmed Amine Jerraya,et al.  Formulation and evaluation of scheduling techniques for control flow graphs , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[5]  Hans Eveking,et al.  Formally Correct Construction of Pipelined Processors , 1998 .

[6]  V. M. Glushkov,et al.  Automata theory and formal microprogram transformations , 1965 .

[7]  Andreas Kuehlmann,et al.  Equivalence checking using cuts and heaps , 1997, DAC.

[8]  David L. Dill,et al.  Automatic verification of Pipelined Microprocessor Control , 1994, CAV.

[9]  Ramayya Kumar,et al.  Applicability of formal synthesis illustrated via scheduling , 1996 .

[10]  Matthias Mutz,et al.  Automatic post-synthesis verification support for a high level synthesis step by using the HOL theorem proving system , 1997, CHARME.

[11]  Ramayya Kumar,et al.  Verification of synthesized circuits at register transfer level with flow graphs , 1991, Proceedings of the European Conference on Design Automation..

[12]  Raul Camposano,et al.  Path-based scheduling for synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Hans Eveking,et al.  Formal synthesis for pipeline design , 1999 .

[14]  Ranga Vemuri,et al.  Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[15]  Arthur J. Bernstein,et al.  Analysis of Programs for Parallel Processing , 1966, IEEE Trans. Electron. Comput..

[16]  Alice C. Parker,et al.  Sehwa: a software package for synthesis of pipelines from behavioral specifications , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Ramayya Kumar,et al.  Formal Synthesis in Circuit Design - A Classification and Survey , 1996, FMCAD.