A bottom-up pattern collapse mitigation strategy for EUV lithography

As the lithographic resolution in semiconductor device manufacturing increases photoresist thickness cannot keep the same pace because of limitations set by pattern transfer. This leads to an increase in aspect ratios of patterned resist structures which in turn gives rise to pattern collapse that prevents the use of the patterned features for pattern transfer. Pattern collapse is caused by the capillary forces present on the resist surface during drying of the wafer. Therefore the best approach for mitigating pattern collapse is the complete removal of any drying steps from the processing of wafers after the lithography has been carried out. Several techniques achieving this have been presented. In this paper we propose a bottom-up strategy for pattern collapse mitigation where the wafers are brought from rinsing to further processing steps while they are still wet, thus avoiding the drying-induced pattern collapse without introducing additional processing steps.