DOIND: a technique for leakage reduction in nanoscale domino logic circuits

A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic.

[1]  Eby G. Friedman,et al.  Domino logic with variable threshold voltage keeper , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Pinaki Mazumder,et al.  On circuit techniques to improve noise immunity of CMOS dynamic logic , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Wuchen Wu,et al.  Low power and high performance dynamic CMOS XOR/XNOR gate design , 2011 .

[4]  K. Asanović,et al.  Leakage-biased domino circuits for dynamic fine-grain leakage reduction , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[5]  Eby G. Friedman,et al.  Sleep switch dual threshold Voltage domino logic with reduced standby leakage current , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  A. Nunez,et al.  Analysis of subthreshold leakage reduction in CMOS digital circuits , 2007, 2007 50th Midwest Symposium on Circuits and Systems.

[7]  R. K. Nagaria,et al.  Leakage Power Analysis of Domino XOR Gate , 2013 .

[8]  J. Kao.  Dual threshold voltage domino logic , 1999, Proceedings of the 25th European Solid-State Circuits Conference.

[9]  Mohamed I. Elmasry,et al.  Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Manisha Pattanaik,et al.  INDEP approach for leakage reduction in nanoscale CMOS circuits , 2015 .

[11]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[12]  Vincent John Mooney,et al.  Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design , 2006, 2006 IFIP International Conference on Very Large Scale Integration.

[13]  A. Peiravi,et al.  A new leakage-tolerant design for high fan-in domino circuits , 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..

[14]  Dhamin Al-Khalili,et al.  UDSM subthreshold leakage model for NMOS transistor stacks , 2008, Microelectron. J..

[15]  Mark C. Johnson,et al.  Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks , 1998, ISLPED '98.

[16]  Kaushik Roy,et al.  Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.

[17]  Vaibhav Neema,et al.  A novel leakage reduction DOIND approach for nanoscale domino logic circuits , 2015, 2015 Eighth International Conference on Contemporary Computing (IC3).