High efficiency 5GHz CMOS power amplifier with adaptive bias control circuit

A 5 GHz automatically bias controlled power amplifier is manufactured in a 0.18 /spl mu/m CMOS process and occupies 0.54 mm/sup 2/. The measured power gain, P/sub 1dB/, and PAE are 7.1 dB, 19.2 dBm, and 17.5%, respectively. For fair comparison, the same PA without the bias circuit is also implemented. The fully integrated bias control circuit improves the power efficiency by 21% at 13 dBm output power. Moreover, the P1dB is also improved from 18.3 dBm to 19.2 dBm.

[1]  B. Wooley,et al.  A CMOS RF power amplifier with parallel amplification for efficient power control , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[2]  P. Asbeck,et al.  An extended Doherty amplifier with high efficiency over a wide power range , 2001, 2001 IEEE MTT-S International Microwave Sympsoium Digest (Cat. No.01CH37157).

[3]  Lawrence E. Larson,et al.  An extended Doherty amplifier with high efficiency over a wide power range , 2001, IMS 2001.

[4]  Peter M. Asbeck,et al.  High-efficiency power amplifier using dynamic power-supply voltage for CDMA applications , 1999 .