HERMES: an infrastructure for low area overhead packet-switching networks on chip

The increasing complexity of integrated circuits drives the research of new on-chip interconnection architectures. A network on chip draws on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. The main goal pursued is to achieve superior bandwidth when compared to conventional on-chip bus architectures. This paper reviews the state of the art in networks on chip. Then, it describes an infrastructure called Hermes, targeted to implement packet-switching mesh and related interconnection architectures and topologies. The basic element of Hermes is a switch with five bi-directional ports, connecting to four other switches and to a local IP core. The switch employs an XY routing algorithm, and uses input queuing. The main design objective was to develop a small size switch, enabling its immediate practical use. The paper also presents the design validation of the Hermes switch and of a network on chip based on it. A Hermes NoC case study has been successfully prototyped in hardware as described in the paper, demonstrating the functionality of the approach. Quantitative data for the Hermes infrastructure is advanced.

[1]  I. Xilinx,et al.  Virtex-II Platform FPGA User Guide , 2002 .

[2]  Prasant Mohapatra,et al.  Wormhole routing techniques for directly connected multicomputer systems , 1998, CSUR.

[3]  Fernando Gehm Moraes,et al.  A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping , 2003, VLSI-SOC.

[4]  Rudy Lauwereins,et al.  Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs , 2002, FPL.

[5]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[6]  Partha Pratim Pande,et al.  Timing analysis of network on chip architectures for MP-SoC platforms , 2005, Microelectron. J..

[7]  Fernando Gehm Moraes,et al.  Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses , 2001, IEEE Trans. Educ..

[8]  Russell Tessier,et al.  ASOC: a scalable, single-chip communications architecture , 2000, Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622).

[9]  David A. Patterson,et al.  Computer architecture (2nd ed.): a quantitative approach , 1996 .

[10]  Sujit Dey,et al.  On-chip communication architecture for OC-768 network processors , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[11]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[12]  Partha Pratim Pande,et al.  Design of a switch for network on chip applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[13]  Jari Nurmi,et al.  Proteo: A New Approach t o Network-on-Chip , 2002 .

[14]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[15]  J.D. Day,et al.  The OSI reference model , 1983 .

[16]  Rudy Lauwereins,et al.  Networks on Chip as Hardware Components of an OS for Reconfigurable Systems , 2003, FPL.

[17]  Kai Hwang,et al.  Advanced computer architecture - parallelism, scalability, programmability , 1992 .

[18]  Lionel M. Ni,et al.  A survey of wormhole routing techniques in direct networks , 1993, Computer.

[19]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[20]  Axel Jantsch,et al.  Networks on chip , 2003 .

[21]  David Notkin,et al.  Computer science in Japanese universities , 1993, Computer.

[22]  Jean-Marc Daveau,et al.  Automating the Design of SOCs Using Cores , 2001, IEEE Des. Test Comput..

[23]  Johnny Öberg,et al.  Lowering power consumption in clock by using globally asynchronous locally synchronous design style , 1999, DAC '99.

[24]  Alberto L. Sangiovanni-Vincentelli,et al.  Addressing the system-on-a-chip interconnect woes through communication-based design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[25]  Alain Greiner,et al.  Micro-network for SoC: implementation of a 32-port SPIN network , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[26]  Kees Goossens,et al.  A Router Architecture for Networks on Silicon , 2001 .

[27]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[28]  Altamiro Amadeu Susin,et al.  SoCIN: a parametric and scalable network-on-chip , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[29]  Luca Benini,et al.  Packetized on-chip interconnect communication analysis for MPSoC , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[30]  Rudy Lauwereins,et al.  Highly scalable network on chip for reconfigurable systems , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).

[31]  Alain Greiner,et al.  SPIN: a scalable, packet switched, on-chip micro-network , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[32]  Partha Pratim Pande,et al.  A scalable communication-centric SoC interconnect architecture , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[33]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[34]  Sujit Dey,et al.  An Interconnect Architecture for Networking Systems on Chips , 2002, IEEE Micro.

[35]  Fernando Gehm Moraes,et al.  From VHDL register transfer level to SystemC transaction level modeling: a comparative case study , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[36]  Dake Liu,et al.  SoCBUS: switched network on chip for hard real time embedded systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[37]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[38]  Martti Forsell,et al.  A Scalable High-Performance Computing Solution for Networks on Chips , 2002, IEEE Micro.

[39]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[40]  Axel Jantsch,et al.  The Nostrum backbone-a communication protocol stack for Networks on Chip , 2004, 17th International Conference on VLSI Design. Proceedings..

[41]  Jari Nurmi,et al.  Buffer implementation for Proteo network-on-chip , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[42]  Yervant Zorian,et al.  Introducing Core-Based System Design , 1997, IEEE Des. Test Comput..