A Multi-Channel Low-Power System-on-Chip for in vivo NeuralSpike Recording

This paper reports a multi-channel neural spike recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 64-channel low-power low-noise analog front-end, a single 8-bit analog-todigital converter (ADC), followed by digital signal compression and transmission units. The 400-MHz transmitter employs a Manchester-Coded Frequency Shift Keying (MC-FSK) modulator with low modulation index. In this way a 1.25-Mbit/s data rate is delivered within a band of about 3 MHz. Compression of the raw data is implemented by detecting the action potentials (APs) and storing 20 samples for each spike waveform. The choice greatly improves data quality and allows single neuron identification. A larger than 10-m transmission range is reached with an overall power consumption of 17.2 mW. This figure translates into a power budget of 269μW per channel, which is in line with the results in literature but allowing a larger transmission distance and more efficient wireless link bandwidth occupation. The implemented IC was mounted on a small and light printed circuit board to be used during neuroscience experiments with freely-behaving rats. Powered by 2 AAA batteries the system can work continuously for more than 100 hours allowing long-lasting neural spike recordings. I. I NTRODUCTION Advanced research in electrophysiology and behavioral neuroscience aims at better understanding brain operation by exploring the complex neural networks in more detail. These investigations are generating an increasing demand f or wireless microsystems capable to record neural signals fro m a large number of implanted electrodes and to deliver data in real time to a remote processing unit. Moreover, as today’s scientific instruments become tomorrow’s medical devices, these systems are seen as a step towards devices for assistin g humans with disabilities (Lebedev et al., 2006). However, a s the number of electrodes increases a huge data throughput is generated calling for a corresponding increase of processi ng frequency, power and RF spectral bandwidth. To cope with this issue two design trends have been followed so far: drastically reducing the throughput, detecting just the o ccurrence time of action potential spikes (Harrison et al., 2007); pushing the throughput to the limits to preserve the entire data content, and either transmitting ultra-wide band puls es (UWB-IR) in the3.1−10.6 GHz with low spectral efficiency (Chae et al., 2008), or using pulse-width modulated (PWM) signals (Lee et al., 2010) to reach a better spectral efficien cy at lower RF frequencies. In (Chae et al., 2008) a 1-GHz band around5 GHz is adopted to transmit short pulses and delivers up to 90-Mbit/s data rate for a 128-channel system, while in (Lee et al., 2010) a FSK modulation at915-MHz carrier frequency transmits 5.5-Mbit/s equivalent throughput within38-MHz band (14% of spectral efficiency) for a 32-channel device. In this fram e our approach was intermediate. The idea of the presents work was to investigate whether data compression can be improved thus making possible to preserve the information needed for single neuron identification while keeping the throughput a nd the bandwidth occupation limited in a few MHz. In addition the transmission range was pushed well beyond the 1-m value reported in above mentioned works to make possible realisti c in-vivo experiments. A valid compression algorithm is the key to reduce the system power consumption allowing long lastin g experiments since the needed transmitted power is directly proportional to the bit rate and to the square of transmissio n distance (Liu et al., 2009). II. SYSTEM DESRIPTION The system consists of a home-made wireless recording unit, a receiver built with off-the-shelf modules plus and a remote host complete of a graphical user interface (GUI) to allow neural signal visualization during in-vivo experiments. A. Wireless recording unit Figure 1 shows the block diagram of the integrated circuit (IC) which acts as recording and transmitting module. The chip, fabricated in0.35−μm CMOS AMS process, occupies a 3.1× 2.7mm area, and is descripted in details in (Bonfanti et al., 2010). The circuit consists of a 64-channel low-noise amplifier array, featuring a pass-band transfer function (t u able high-pass and 10-kHz low-pass cut-off frequencies) and about 3−μVrms input referred noise. The amplifier outputs are sampled by a time-division multiplexer (TDM) at 20 kS/s onto one data lead before being further amplified by a variable-gain amplifier (VGA) and converted by an 8-bit successive approximation register analog to digital conve rter (SAR ADC). The data throughput at the ADC output is 10.24 Mbit/s. The digital data are then processed by a logic block, performing data compression, assembly and Manchest er encoding of the bit stream. Data compression, that is briefly described in Sect. III, allows a reduction of data throughpu t by a factor of10, generating a bit stream of 1.25 Mbit/s that is sent to the modulator. The transmitter consists of a volta gecontrolled oscillator (VCO) directly modulated by the digi tal data. To squeeze spectrum occupation into 3-MHz bandwidth, a Manchester-coded FSK modulation with low modulation index (peak-to-peak frequency deviation of 800 kHz) has been adopted. In order to prevent drifts of the 400-MHz RF carrier