Semiconductor memory device having otp cell array

Disclosed is a semiconductor memory device including an OTP cell array, a convergence unit, and a sense amplifier. The semiconductor memory device according to an embodiment of the present invention can include an OTP cell array including OTP cells and bit-lines. The OTP cell array outputs signals corresponding to the bit-data stored in the OTP cells through the bit-lines. The convergence unit transmits signals of one or more bit-lines among the multiple bit-lines to the sense amplifier. The convergence unit, according to the embodiments of the present invention, can be controlled by addresses and include coupling nodes connecting multiple bit-lines.