Improved Contacts to MoS2 Transistors by Ultra-High Vacuum Metal Deposition.

The scaling of transistors to sub-10 nm dimensions is strongly limited by their contact resistance (RC). Here we present a systematic study of scaling MoS2 devices and contacts with varying electrode metals and controlled deposition conditions, over a wide range of temperatures (80 to 500 K), carrier densities (10(12) to 10(13) cm(-2)), and contact dimensions (20 to 500 nm). We uncover that Au deposited in ultra-high vacuum (∼10(-9) Torr) yields three times lower RC than under normal conditions, reaching 740 Ω·μm and specific contact resistivity 3 × 10(-7) Ω·cm(2), stable for over four months. Modeling reveals separate RC contributions from the Schottky barrier and the series access resistance, providing key insights on how to further improve scaling of MoS2 contacts and transistor dimensions. The contact transfer length is ∼35 nm at 300 K, which is verified experimentally using devices with 20 nm contacts and 70 nm contact pitch (CP), equivalent to the "14 nm" technology node.

[1]  Y. Tosaka,et al.  Scaling theory for double-gate SOI MOSFET's , 1993 .

[2]  S. Lodha,et al.  Evaluating Au and Pd contacts in mono and multilayer MoS2 transistors , 2014, 72nd Device Research Conference.

[3]  A. Javey,et al.  High-performance single layered WSe₂ p-FETs with chemically doped contacts. , 2012, Nano letters.

[4]  Mobility modelling of SOI MOSFETs , 2004 .

[5]  Gautam Gupta,et al.  Phase-engineered low-resistance contacts for ultrathin MoS2 transistors. , 2014, Nature materials.

[6]  J. Appenzeller,et al.  Where does the current flow in two-dimensional layered systems? , 2013, Nano letters.

[7]  S. T. Ng,et al.  Impact of surface roughness on silicon and germanium ultra-thin-body MOSFETs , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[8]  H. Sakaki,et al.  Interface roughness scattering in GaAs/AlAs quantum wells , 1987 .

[9]  M. Fischetti,et al.  Modeling of Surface-Roughness Scattering in Ultrathin-Body SOI MOSFETs , 2007, IEEE Transactions on Electron Devices.

[10]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[11]  Debdeep Jena,et al.  Tunneling Transistors Based on Graphene and 2-D Crystals , 2013, Proceedings of the IEEE.

[12]  T. Hiramoto,et al.  Impact of SOI thickness fluctuation on threshold voltage variation in ultra-thin body SOI MOSFETs , 2005, IEEE Transactions on Nanotechnology.

[13]  Rodney S. Ruoff,et al.  Correction factors for 4-probe electrical measurements with finite size electrodes and material anisotropy: a finite element study , 2007 .

[14]  Jonghwa Eom,et al.  High-mobility and air-stable single-layer WS2 field-effect transistors sandwiched between chemical vapor deposition-grown hexagonal BN films , 2015, Scientific Reports.

[15]  D. Pearman Electrical Characterisation and Modelling of Schottky barrier metal source/drain MOSFETs , 2007 .

[16]  P. Avouris,et al.  Carrier scattering, mobilities, and electrostatic potential in monolayer, bilayer, and trilayer graphene , 2009, 0908.0749.

[17]  T. Skotnicki,et al.  The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance , 2005, IEEE Circuits and Devices Magazine.

[18]  Towards intrinsic charge transport in monolayer molybdenum disulfide by defect and interface engineering. , 2014, Nature communications.

[19]  Bin Liu,et al.  Hysteresis in single-layer MoS2 field effect transistors. , 2012, ACS nano.

[20]  Wilman Tsai,et al.  Chloride molecular doping technique on 2D materials: WS2 and MoS2. , 2014, Nano letters.

[21]  A. Hikavyy,et al.  Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography , 2007, 2007 IEEE Symposium on VLSI Technology.

[22]  P. Ye,et al.  Molecular Doping of Multilayer ${\rm MoS}_{2}$ Field-Effect Transistors: Reduction in Sheet and Contact Resistances , 2013, IEEE Electron Device Letters.

[23]  Tobin J Marks,et al.  Low-frequency electronic noise in single-layer MoS2 transistors. , 2013, Nano letters.

[24]  Tomonori Nishimura,et al.  Mobility Variations in Mono- and Multi-Layer Graphene Films , 2009 .

[25]  A. Radenović,et al.  Single-layer MoS2 transistors. , 2011, Nature nanotechnology.

[26]  K. Banerjee,et al.  High-Performance Field-Effect-Transistors On Monolayer-WSe2 , 2013 .

[27]  S. Ghatak,et al.  Observation of trap-assisted space charge limited conductivity in short channel MoS2 transistor , 2013, 1308.4858.

[28]  Ching-Te Chuang,et al.  Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap , 2009, IEEE Transactions on Electron Devices.

[29]  K. Banerjee,et al.  High-performance few-layer-MoS2 field-effect-transistor with record low contact-resistance , 2013, 2013 IEEE International Electron Devices Meeting.

[30]  T. Numata,et al.  Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm , 2002, Digest. International Electron Devices Meeting,.

[31]  Kinam Kim,et al.  High-mobility and low-power thin-film transistors based on multilayer MoS2 crystals , 2012, Nature Communications.

[32]  J.L. Hoyt,et al.  Thickness Dependence of Hole Mobility in Ultrathin SiGe-Channel p-MOSFETs , 2008, IEEE Transactions on Electron Devices.

[33]  J. Jopling,et al.  High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[34]  L. Esaki,et al.  Tunneling in a finite superlattice , 1973 .

[35]  Junji Koga,et al.  Experimental study on carrier transport mechanisms in double- and single-gate ultrathin-body MOSFETs - Coulomb scattering, volume inversion, and /spl delta/T/sub SOI/-induced scattering , 2003, IEEE International Electron Devices Meeting 2003.

[36]  L. Selmi,et al.  Mobility extraction in SOI MOSFETs with sub 1 nm body thickness , 2009 .

[37]  B. Radisavljevic,et al.  Mobility engineering and a metal-insulator transition in monolayer MoS₂. , 2013, Nature materials.

[38]  Krishna C. Saraswat,et al.  Limits of specific contact resistivity to Si, Ge and III-V semiconductors using interfacial layers , 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

[39]  Improved fin width scaling in fully-depleted FinFETs by source-drain implant optimization , 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

[40]  L. Gomez,et al.  Electron Transport in Strained-Silicon Directly on Insulator Ultrathin-Body n-MOSFETs With Body Thickness Ranging From 2 to 25 nm , 2007, IEEE Electron Device Letters.

[41]  Band-like transport in high mobility unencapsulated single-layer MoS 2 transistors , 2013, 1304.5567.

[42]  Horst H. Berger,et al.  Models for contacts to planar devices , 1972 .

[43]  R. M. Swanson,et al.  Modeling and measurement of contact resistances , 1987, IEEE Transactions on Electron Devices.

[44]  Mark Y. Liu,et al.  A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size , 2014, 2014 IEEE International Electron Devices Meeting.

[45]  A. Javey,et al.  Air-stable surface charge transfer doping of MoS₂ by benzyl viologen. , 2014, Journal of the American Chemical Society.

[46]  K. Tsukagoshi,et al.  Thickness-dependent interfacial Coulomb scattering in atomically thin field-effect transistors. , 2013, Nano letters.

[47]  D. Schroder Semiconductor Material and Device Characterization , 1990 .

[48]  Ching-Te Chuang,et al.  The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology , 2007, IEEE Transactions on Electron Devices.

[49]  P. Ye,et al.  Metal contacts to MoS2: A two-dimensional semiconductor , 2012, 70th Device Research Conference.