Ultra low voltage high speed 1-bit CMOS adder

In this paper, we present a novel design for realize full adder circuit. Our approach based on XOR-XNOR design full adder circuits in a single unit. Objective of this work is to investigate the power, delay and power delay product of low voltage full adder cells in different CMOS logic styles. Simulation results illustrate the superiority of the proposed adder circuit against the conventional CMOS, Hybrid, Bridge, Xor-Xnor adder circuits in terms of power, delay, PDP. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. The performance of the full adder circuits is based on GPDK 90nm CMOS process models at all range of the supply voltage starting from 0.65V to 1.5V evaluated by the comparison of the simulation results obtained from Cadence. Simulation results reveal that the proposed circuit exhibits lower PDP and is faster when compared with available 1-bit full adder circuits. To summarize, some performance criteria are considered in the design and evaluation of adder cells, of which some are at ease of design, robustness, silicon area, delay, and power consumption. The design is implemented on GDPK 90 nm process models in Cadence Virtuoso Schematic Composer at 1.5V single ended supply voltage and simulations are carried out on Spectre S.

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